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    Insulative covering of probe tips
    121.
    发明申请
    Insulative covering of probe tips 有权
    探头尖端的绝缘覆盖

    公开(公告)号：US20040266234A1

    公开(公告)日：2004-12-30

    申请号：US10607628

    申请日：2003-06-27

    Applicant: FormFactor, Inc.

    Inventor： Gary W. Grube

    IPC: H01R013/44

    CPC classification number: H01R13/2442 ,  G01R1/07342 ,  H01R12/7076 ,  H01R13/2464 ,  H01R13/447

    Abstract: An insulative material is applied to one or more selected probe tips to disable those probes, and the probes are brought into contact with a semiconductor die. One or more tests are run on the die to verify sufficient testing of the die without the disabled probes. The process may be repeated with other probes disabled to determine which probes need not be used in testing the die.

    Abstract translation: 将绝缘材料施加到一个或多个所选择的探针尖端以禁用那些探针，并且使探针与半导体管芯接触。 在芯片上运行一个或多个测试，以验证芯片的充分测试，而不使用禁用的探针。 可以重复该过程，其他探针被禁用以确定哪些探针不需要用于测试模具。

    Microelectronic contact structures, and methods of making same
    124.
    发明申请
    Microelectronic contact structures, and methods of making same 审中-公开
    微电子接触结构及其制造方法

    公开(公告)号：US20040072452A1

    公开(公告)日：2004-04-15

    申请号：US10692174

    申请日：2003-10-23

    Applicant: FormFactor, Inc.

    Inventor： Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu

    IPC: H01R012/00

    CPC classification number: G01R1/07314 ,  H01H1/0036 ,  H01L2224/02335 ,  H01L2924/00013 ,  Y10T29/49147 ,  Y10T29/49204 ,  Y10T29/49218 ,  Y10T29/49316 ,  H01L2224/13099

    Abstract: Microelectronic contact structures are fabricated by separately forming, then joining together, various components thereof. Each contact structure has three components: a nullpostnull component, a nullbeamnull component, and a nulltipnull component. The resulting contact structure, mounted to an electronic component, is useful for making an electrical connection with another electronic component. The post component can be fabricated on a sacrificial substrate, joined to the electronic component and its sacrificial substrate removed. Alternatively, the post component can be formed on the electronic component. The beam and tip components can each be fabricated on a sacrificial substrate. The beam component is joined to the post component and its sacrificial substrate is removed, and the tip component is joined to the beam component and its sacrificial substrate is removed.

    Abstract translation: 微电子接触结构通过分别形成，然后连接在一起而制成其各种部件。 每个接触结构具有三个部件：“后”部件，“梁”部件和“尖端”部件。 安装到电子部件上的所得接触结构对于与另一个电子部件进行电连接是有用的。 后部组件可以制造在牺牲基板上，连接到电子部件并且去除其牺牲基板。 或者，可以在电子部件上形成柱部件。 梁和尖端部件可以分别制造在牺牲衬底上。 梁组件连接到柱部件，并且其牺牲基板被移除，并且尖端部件接合到梁部件并且其牺牲基板被移除。

    Process and apparatus for finding pahts through a routing space
    126.
    发明申请
    Process and apparatus for finding pahts through a routing space 失效
    用于通过路由空间寻找朋友的过程和设备

    公开(公告)号：US20030070153A1

    公开(公告)日：2003-04-10

    申请号：US09938789

    申请日：2001-08-24

    Applicant: FormFactor, Inc.

    Inventor： Mac Stevens ,  Yves Parent

    IPC: G06F017/50

    CPC classification number: G06F17/5077

    Abstract: An initial graph of nodes is created within a routing space, and the number and locations of the nodes in the graph are adjusted. Links are created between nodes of the graph, and traces between specified nodes are created through the linked graph.

    Abstract translation: 在路由空间内创建节点的初始图，并调整图中节点的数量和位置。 在图的节点之间创建链接，并通过链接图创建指定节点之间的跟踪。

    Method and system for designing a probe card
    127.
    发明申请
    Method and system for designing a probe card 失效

    公开(公告)号：US20030055736A1

    公开(公告)日：2003-03-20

    申请号：US09954617

    申请日：2001-09-17

    Applicant: FormFactor, Inc.

    Inventor： Benjamin N. Eldridge ,  Mark W. Brandemuehl ,  Stefan Graef ,  Yves Parent

    IPC: G06F017/60

    CPC classification number: G01R3/00 ,  G01R1/073 ,  G01R1/07342 ,  G06Q30/0609 ,  G06Q30/0621 ,  G06Q30/0633 ,  G06Q50/188

    Abstract: A method and system for designing a probe card from data provided by prospective customers via the Internet is provided. Design specifications are entered into the system by prospective customers and compiled into a database. The collective feasibility of each set of design specifications is determined by an automated computer system and communicated to the prospective customer. If feasible, additional software enables prospective customers to create verification packages according to their respective design specifications. These verification packages further consist of drawing files visually describing the final design and verification files confirming wafer bonding pad data. Verification packages are reviewed and forwarded to an applications engineer after customer approval. An interactive simulation of probe card performance is also provided. Data on probe card performance is incorporated into an overall modeling exercise, which includes not only the probe card, but data on the device(s) under test and wafer, as well as data on automated test equipment.

    Apparatus for reducing power supply noise in an integrated circuit
    130.
    发明申请
    Apparatus for reducing power supply noise in an integrated circuit 有权
    用于降低集成电路中电源噪声的装置

    公开(公告)号：US20020125904A1

    公开(公告)日：2002-09-12

    申请号：US10062999

    申请日：2002-01-30

    Applicant: FormFactor, Inc.

    Inventor： Benjamin N. Eldridge ,  Charles A. Miller

    IPC: G01R031/26

    CPC classification number: G01R31/31721 ,  G01R31/2851 ,  G01R31/31905 ,  G01R31/31924 ,  G06F1/26

    Abstract: A power supply provides power to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal may temporarily increase due, for example, to state changes in the DUT. To limit variation (noise) in voltage at the power input terminal, a supplemental current is supplied to the power input terminal.

    Abstract translation: 电源为被测集成电路设备（DUT）的电源端子供电。 DUT在电源输入端子上对电流的需求可能由于例如DUT的状态变化而暂时增加。 为了限制电源输入端子电压的变化（噪声），补充电流被提供给电源输入端子。

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