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公开(公告)号:US09142533B2
公开(公告)日:2015-09-22
申请号:US12784266
申请日:2010-05-20
申请人: Wen-Wei Shen , Ying-Ching Shih , Chen-Shien Chen , Ming-Fa Chen
发明人: Wen-Wei Shen , Ying-Ching Shih , Chen-Shien Chen , Ming-Fa Chen
IPC分类号: H01L25/065 , H01L25/00 , H01L23/498 , H01L23/31 , H01L23/00
CPC分类号: H01L25/0657 , H01L21/486 , H01L23/3114 , H01L23/3192 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/5384 , H01L24/03 , H01L24/05 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/81 , H01L25/0655 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/0381 , H01L2224/03831 , H01L2224/0401 , H01L2224/0557 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/1162 , H01L2224/11622 , H01L2224/1181 , H01L2224/11849 , H01L2224/11903 , H01L2224/13016 , H01L2224/13025 , H01L2224/13084 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13155 , H01L2224/13169 , H01L2224/1354 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81193 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06568 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H01L2224/05552 , H01L2924/00
摘要: A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.
摘要翻译: 提供了可用于将一个衬底互连到另一衬底的凸块结构。 导电柱形成在第一基板上,使得导电柱的宽度不同于第二基板上的接触表面。 在一个实施例中,第一基板的导电柱具有梯形形状或具有锥形侧壁的形状,从而提供具有比尖端部宽的基部的导电柱。 基板可以各自为集成电路管芯,插入件,印刷电路板,高密度互连等。
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公开(公告)号:US09093332B2
公开(公告)日:2015-07-28
申请号:US13023011
申请日:2011-02-08
申请人: Tin-Hao Kuo , Yu-Feng Chen , Chen-Shien Chen , Chen-Hua Yu , Sheng-Yu Wu , Chita Chuang
发明人: Tin-Hao Kuo , Yu-Feng Chen , Chen-Shien Chen , Chen-Hua Yu , Sheng-Yu Wu , Chita Chuang
CPC分类号: H01L24/13 , H01L23/3192 , H01L24/05 , H01L24/14 , H01L2224/0401 , H01L2224/05555 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05687 , H01L2224/1145 , H01L2224/11452 , H01L2224/13012 , H01L2224/13014 , H01L2224/13022 , H01L2224/13027 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/14141 , H01L2224/81192 , H01L2924/00013 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/0105 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012 , H01L2924/00
摘要: An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump.
摘要翻译: 提供了用于半导体器件的细长凸块结构。 最上面的保护层具有通过其形成的开口。 在该开口内形成一个支柱,并延伸至最上层保护层的至少一部分。 在最上保护层上延伸的部分呈现大致细长的形状。 在一个实施例中,开口相对于在最上保护层上延伸的凸起结构的部分的位置使得从开口的边缘到凸起的边缘的距离的比例大于或等于约 0.2。 在另一个实施例中,开口的位置相对于凸块的中心偏移。
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公开(公告)号:US08932906B2
公开(公告)日:2015-01-13
申请号:US12193950
申请日:2008-08-19
申请人: Dean Wang , Chen-Shien Chen , Kai-Ming Ching , Bo-I Lee , Chien-Hsiun Lee
发明人: Dean Wang , Chen-Shien Chen , Kai-Ming Ching , Bo-I Lee , Chien-Hsiun Lee
CPC分类号: H01L25/0657 , H01L21/187 , H01L23/481 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/05124 , H01L2224/05147 , H01L2224/05573 , H01L2224/13 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16113 , H01L2224/16146 , H01L2224/73103 , H01L2224/73204 , H01L2224/81 , H01L2224/81193 , H01L2225/06513 , H01L2225/06541 , H01L2924/06 , H01L2924/07025 , H01L2924/00014
摘要: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.
摘要翻译: 提出了用于接合半导体衬底的系统和方法。 优选实施例包括在半导体衬底的表面上形成缓冲层,同时保留从缓冲层突出的TSV,以便防止可能形成的潜在的空隙。 在与第一半导体衬底接合的另一个半导体衬底上形成保护层。 两个基板对准并结合在一起,缓冲层防止与原始半导体衬底的表面的任何短路接触。
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公开(公告)号:US08922006B2
公开(公告)日:2014-12-30
申请号:US13559840
申请日:2012-07-27
申请人: Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
发明人: Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
IPC分类号: H01L23/488
CPC分类号: H01L23/3192 , H01L23/293 , H01L23/49811 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05005 , H01L2224/05015 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/13012 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2924/00014 , H01L2924/01029 , H01L2924/00012 , H01L2924/206 , H01L2924/01047
摘要: A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 μm. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer.
摘要翻译: 一种器件包括衬底,衬底上的金属焊盘以及覆盖金属焊盘的边缘部分的钝化层。 钝化层具有与金属焊盘重叠的第一开口,其中第一开口具有在平行于衬底的主表面的方向上测量的第一横向尺寸。 聚合物层在钝化层上方并覆盖金属焊盘的边缘部分。 聚合物层具有与金属垫重叠的第二开口。 第二开口具有在该方向上测量的第二横向尺寸。 第一横向尺寸大于第二横向尺寸大于约7μm。 下冲击冶金(UBM)包括第二开口中的第一部分和覆盖聚合物层部分的第二部分。
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公开(公告)号:US08859424B2
公开(公告)日:2014-10-14
申请号:US12840903
申请日:2010-07-21
申请人: Yung-Jean Lu , Ming-Fa Chen , Chen-Shien Chen , Jao Sheng Huang
发明人: Yung-Jean Lu , Ming-Fa Chen , Chen-Shien Chen , Jao Sheng Huang
IPC分类号: H01L21/44 , H01L21/683
CPC分类号: H01L21/6833 , Y10T29/49124
摘要: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.
摘要翻译: 公开了一种用于半导体晶片载体的系统和方法。 一个实施方案包括半导体晶片载体,其中将导电掺杂剂注入到载体中,以便放大静电卡盘和载体之间的库仑力,以补偿由较薄的半导体晶片产生的减小的力。 另一个实施例在载体内形成导电层和通孔,而不是注入导电掺杂剂。
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公开(公告)号:US08759949B2
公开(公告)日:2014-06-24
申请号:US12708287
申请日:2010-02-18
申请人: Chen-Hua Yu , Hon-Lin Huang , Kuo-Ching Hsu , Chen-Shien Chen
发明人: Chen-Hua Yu , Hon-Lin Huang , Kuo-Ching Hsu , Chen-Shien Chen
CPC分类号: H01L23/481 , H01L21/6836 , H01L21/76898 , H01L23/525 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0231 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05567 , H01L2224/05568 , H01L2224/11002 , H01L2224/11462 , H01L2224/1147 , H01L2224/13023 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13171 , H01L2224/13172 , H01L2224/13184 , H01L2224/13583 , H01L2224/13655 , H01L2224/81001 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014 , H01L2224/13099 , H01L2224/05552
摘要: An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.
摘要翻译: 集成电路结构包括具有前侧和后侧的半导体衬底以及穿透半导体衬底的导电通路。 导电通孔包括延伸到半导体衬底背面的后端。 再分配线(RDL)位于半导体衬底的背面并电连接到导电通孔的后端。 钝化层在RDL上方,在钝化层中具有开口,其中RDL的一部分通过开口露出。 铜柱在开口中具有一部分并与RDL电连接。
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公开(公告)号:US20130147030A1
公开(公告)日:2013-06-13
申请号:US13313333
申请日:2011-12-07
申请人: Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen
发明人: Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen
IPC分类号: H01L23/498
CPC分类号: H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05016 , H01L2224/05022 , H01L2224/05572 , H01L2224/13014 , H01L2224/13015 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16225 , H01L2224/81191 , H01L2224/81385 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/05552 , H01L2224/81805
摘要: A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The metal trace includes a portion having an edge, wherein the edge is not parallel to the lengthwise direction of the metal trace. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface and the edge of the portion of the metal trace.
摘要翻译: 一种装置包括第一和第二包装部件。 金属迹线设置在第一包装部件的表面上。 金属迹线具有长度方向。 金属迹线包括具有边缘的部分,其中边缘不平行于金属迹线的长度方向。 第二包装部件包括金属支柱,其中第二包装部件设置在第一包装部件上。 焊接区域将金属柱粘合到金属迹线,其中焊料区域接触金属迹线的顶部表面和边缘。
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公开(公告)号:US20130026614A1
公开(公告)日:2013-01-31
申请号:US13426386
申请日:2012-03-21
申请人: Chen-Hua Yu , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii , Sheng-Yu Wu , Yen-Liang Lin
发明人: Chen-Hua Yu , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii , Sheng-Yu Wu , Yen-Liang Lin
IPC分类号: H01L23/495 , H01L21/98
CPC分类号: H01L23/49811 , H01L21/76885 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L2224/1145 , H01L2224/1146 , H01L2224/13005 , H01L2224/13012 , H01L2224/13014 , H01L2224/13017 , H01L2224/13082 , H01L2224/13083 , H01L2224/13147 , H01L2224/16238 , H01L2924/1306 , H01L2924/00014 , H01L2924/00012 , H01L2924/206 , H01L2924/00
摘要: The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.
摘要翻译: 本发明提供集成电路。 集成电路包括形成在基板上的互连结构; 形成在所述互连结构上并联接到所述互连结构的着陆金属迹线,其中所述着陆金属迹线包括沿第一方向限定的第一宽度T; 以及形成在所述着陆金属迹线上并与所述着陆金属迹线对准的金属凸块柱,其中所述金属凸块柱包括在所述第一方向上限定的第二宽度U,并且所述第二宽度U大于所述第一宽度T.
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公开(公告)号:US08158456B2
公开(公告)日:2012-04-17
申请号:US12329341
申请日:2008-12-05
申请人: Ming-Fa Chen , Chen-Shien Chen , Wen-Chih Chiu
发明人: Ming-Fa Chen , Chen-Shien Chen , Wen-Chih Chiu
IPC分类号: H01L21/02
CPC分类号: H01L21/76898 , H01L21/6835 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/034 , H01L2224/0361 , H01L2224/03616 , H01L2224/0401 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/13009 , H01L2224/13025 , H01L2224/131 , H01L2224/13109 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13184 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/81801 , H01L2224/9202 , H01L2224/9222 , H01L2224/92222 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/14 , H01L2224/81 , H01L2224/80 , H01L2924/00014 , H01L2924/0105 , H01L2924/01079 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2924/00012 , H01L2924/00
摘要: The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wafer substrate. The method generally reduces the risk of overly-thinning a wafer substrate in a wafer back-side grinding process typically used to expose and make electrical contacts to the TSVs. By providing deeper TSVs and bonding pads, individual wafers and dies may be bonded directly between the TSVs and bonding pads on an additional wafer.
摘要翻译: 描述了在集成电路(IC)裸片或晶片中通过硅通孔(TSV)的形成,其中在金属化处理之前的集成工艺中形成TSV。 TSV可以以增加的纵横比制造,在晶片衬底中更深地延伸。 该方法通常降低了通常用于暴露并与TSV的电接触的晶片背面研磨工艺中的晶片衬底过度稀化的风险。 通过提供更深的TSV和接合焊盘,单个晶片和管芯可以直接接合在TSV和附加晶片上的焊盘之间。
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160.
公开(公告)号:US20110165776A1
公开(公告)日:2011-07-07
申请号:US13050424
申请日:2011-03-17
申请人: Kuo-Ching Hsu , Chen-Shien Chen , Hon-Lin Huang
发明人: Kuo-Ching Hsu , Chen-Shien Chen , Hon-Lin Huang
IPC分类号: H01L21/768
CPC分类号: H01L24/11 , H01L23/481 , H01L24/05 , H01L24/12 , H01L2224/0231 , H01L2224/02311 , H01L2224/02372 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/13024 , H01L2224/13027 , H01L2224/13099 , H01L2224/13155 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.
摘要翻译: 集成电路结构包括具有正面和背面的半导体衬底。 穿透硅通孔(TSV)穿透半导体衬底,其中TSV具有延伸到半导体衬底背面的后端。 再分配线(RDL)形成在半导体衬底的背面上并连接到TSV的后端。 钝化层在RDL上方,其中在钝化层中形成有开口,其中RDL的顶表面的一部分和RDL的侧壁通过开口露出。 在开口处形成金属表面,并与RDL的顶表面和侧壁的部分接触。
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