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公开(公告)号：US20180033757A1
公开(公告)日：2018-02-01
申请号：US15720127
申请日：2017-09-29
Applicant: Renesas Electronics Corporation
Inventor： Akira YAJIMA
IPC: H01L23/00
CPC classification number: H01L24/14 , H01L23/3192 , H01L23/525 , H01L23/53214 , H01L23/53228 , H01L23/5329 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/02331 , H01L2224/02377 , H01L2224/0239 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03614 , H01L2224/03914 , H01L2224/0401 , H01L2224/05024 , H01L2224/05073 , H01L2224/0508 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05187 , H01L2224/05664 , H01L2224/10126 , H01L2224/10145 , H01L2224/11334 , H01L2224/11849 , H01L2224/119 , H01L2224/11901 , H01L2224/13017 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14051 , H01L2224/14131 , H01L2224/14133 , H01L2224/14135 , H01L2224/14177 , H01L2224/14179 , H01L2224/14517 , H01L2224/16058 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/17051 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81139 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/814 , H01L2224/81411 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2924/0132 , H01L2924/0133 , H01L2924/07025 , H01L2924/15311 , H01L2924/351 , H01L2924/381 , H01L2924/00012 , H01L2924/014 , H01L2924/0665 , H01L2924/01022 , H01L2924/04941 , H01L2924/01029 , H01L2924/01028 , H01L2924/01074 , H01L2924/01024 , H01L2924/01073 , H01L2924/0496 , H01L2924/01046 , H01L2924/01044 , H01L2924/01078 , H01L2924/01047 , H01L2924/00014 , H01L2924/00
Abstract: In the semiconductor device, a bump electrode which connects a semiconductor chip and a wiring board is made up of a first part surrounded by an insulating film and a second part exposed from the insulating film. Since it is possible to reduce a width of the bump electrode while increasing a height of the bump electrode, a distance between the neighboring bump electrodes can be increased, and a filling property of a sealing material can be improved.
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12.发明申请公开(公告)号：US20170062361A1
公开(公告)日：2017-03-02
申请号：US15186903
申请日：2016-06-20
Applicant: Renesas Electronics Corporation
Inventor： Akira YAJIMA
IPC: H01L23/00
CPC classification number: H01L24/02 , H01L23/293 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/02315 , H01L2224/02331 , H01L2224/0236 , H01L2224/02373 , H01L2224/0239 , H01L2224/024 , H01L2224/04042 , H01L2224/05008 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05176 , H01L2224/05181 , H01L2224/05184 , H01L2224/05644 , H01L2224/4502 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2924/01029 , H01L2924/07025 , H01L2924/364 , H01L2924/365 , H01L2924/00014 , H01L2924/00015 , H01L2924/01007 , H01L2924/01074 , H01L2924/01014 , H01L2924/013 , H01L2924/00013
Abstract: Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.
Abstract translation: 提高了半导体器件的可靠性。 在再分配层的互连宽度方向的剖视图中，在互连沟槽的侧面上设置斜面。 互连宽度方向上的互连沟槽的最大开口宽度大于互连宽度方向上的再分配层的最大互连宽度，并且设置互连沟槽以在平面图中封装再分配层。
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Patent Agency Ranking
公开(公告)号：US20170062292A1
公开(公告)日：2017-03-02
申请号：US15245700
申请日：2016-08-24
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Akira YAJIMA
IPC: H01L21/66 , H01L21/324 , H01L21/4763 , H01L23/00 , H01L25/065
CPC classification number: H01L22/32 , G11C29/06 , G11C29/48 , G11C2029/5602 , H01L21/324 , H01L21/47635 , H01L22/14 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/43 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L25/0655 , H01L25/0657 , H01L2224/02311 , H01L2224/02331 , H01L2224/02377 , H01L2224/03009 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05186 , H01L2224/05548 , H01L2224/05554 , H01L2224/05567 , H01L2224/05583 , H01L2224/05655 , H01L2224/05686 , H01L2224/06102 , H01L2224/13021 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/16145 , H01L2224/451 , H01L2224/48091 , H01L2224/48138 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2924/04941 , H01L2924/00014 , H01L2924/014
Abstract: To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.
Abstract translation: 为了通过抑制半导体器件的测试中的焊料的不良接合来提高测试的可靠性，制造半导体器件的方法包括：制备半导体晶片，其包括设置有第一盖膜的第一焊盘电极和第二焊盘 电极，设置有第二盖膜。 此外，形成包括第一焊盘电极上的第一开口和第二焊盘电极上的第二开口的聚酰亚胺层，然后形成经由第二开口连接到第二焊盘电极的重排布线。 接下来，在聚酰亚胺层中形成开口，使得有机反应层保留在重排布线的第一焊盘电极和凸起焊盘的每一个上，然后对半导体晶片进行热处理，然后形成凸块 在重新布线上。
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公开(公告)号：US20170033074A1
公开(公告)日：2017-02-02
申请号：US15293549
申请日：2016-10-14
Applicant: Renesas Electronics Corporation
Inventor： Akira YAJIMA
IPC: H01L23/00
CPC classification number: H01L24/45 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/43 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/02166 , H01L2224/02317 , H01L2224/0235 , H01L2224/0237 , H01L2224/02373 , H01L2224/0239 , H01L2224/024 , H01L2224/04042 , H01L2224/05024 , H01L2224/05082 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/0519 , H01L2224/05644 , H01L2224/0603 , H01L2224/43985 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48463 , H01L2224/49175 , H01L2224/4941 , H01L2225/06506 , H01L2225/06527 , H01L2924/01047 , H01L2924/13091 , H01L2924/00014
Abstract: A semiconductor device includes an opening and a redistribution layer gutter which are formed integrally in a polyimide resin film of a single layer. A redistribution layer is formed in the polyimide resin film of a single layer. A wiring material (silver) including the redistribution layer can be inhibited from migrating.
Abstract translation: 半导体器件包括在单层的聚酰亚胺树脂膜中整体形成的开口和再分布层沟槽。 在单层的聚酰亚胺树脂膜中形成再分布层。 可以抑制包含再分配层的布线材料（银）的迁移。
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公开(公告)号：US20160322321A1
公开(公告)日：2016-11-03
申请号：US15097111
申请日：2016-04-12
Applicant: Renesas Electronics Corporation
Inventor： Akira YAJIMA , Hideki HARANO , Katsuhiro TORII , Hironori OCHI
CPC classification number: H01L24/13 , H01L21/563 , H01L23/3128 , H01L24/11 , H01L2224/11019 , H01L2224/11462 , H01L2224/11849 , H01L2224/13014 , H01L2224/13017 , H01L2224/13026 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13551 , H01L2224/13564 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/0133 , H01L2924/014 , H01L2924/15311 , H01L2924/3512
Abstract: A semiconductor device includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, a post electrode formed on the pad electrode and made of a copper film, a solder ball electrode formed on the post electrode and made of ternary alloy containing tin, a terminal connected to the solder ball electrode and formed on a front surface of a wiring board, and a sealing material filling a gap between the semiconductor substrate and the wiring board. The post electrode includes a cylindrical stem portion and an overhanging portion positioned in an upper part of the stem portion and protruding to an outer side of the stem portion, the solder ball electrode is connected to an upper surface of the post electrode over the stem portion and the overhanging portion, and a sidewall of the stem portion contacts with the sealing material over the entire circumference thereof.
Abstract translation: 半导体器件包括半导体衬底，形成在半导体衬底上的焊盘电极，形成在焊盘电极上并由铜膜制成的焊接电极，形成在焊后电极上并由含锡的三元合金制成的焊球电极， 端子连接到焊球电极并形成在布线板的前表面上，以及填充半导体衬底和布线板之间的间隙的密封材料。 柱电极包括圆柱形杆部分和位于杆部分的上部中并突出到杆部分的外侧的悬伸部分，焊球电极连接到柱塞电极的上表面上， 并且突出部分，并且杆部分的侧壁在其整个圆周上与密封材料接触。
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公开(公告)号：US20160240484A1
公开(公告)日：2016-08-18
申请号：US15139825
申请日：2016-04-27
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hisao SHIGIHARA , Hiromi SHIGIHARA , Akira YAJIMA , Hiroshi TSUKAMOTO
IPC: H01L23/532 , H01L23/29 , H01L23/00
CPC classification number: H01L23/53238 , H01L21/4885 , H01L23/293 , H01L23/3192 , H01L23/4952 , H01L23/49811 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/43 , H01L24/45 , H01L24/46 , H01L24/48 , H01L24/85 , H01L24/94 , H01L2224/02311 , H01L2224/02313 , H01L2224/02373 , H01L2224/02377 , H01L2224/02379 , H01L2224/0239 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/03474 , H01L2224/0361 , H01L2224/03914 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05084 , H01L2224/05147 , H01L2224/05155 , H01L2224/05171 , H01L2224/05548 , H01L2224/05552 , H01L2224/05569 , H01L2224/05644 , H01L2224/05664 , H01L2224/06135 , H01L2224/06138 , H01L2224/131 , H01L2224/13144 , H01L2224/16245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/48644 , H01L2224/48664 , H01L2224/48844 , H01L2224/48864 , H01L2224/85181 , H01L2224/94 , H01L2924/00 , H01L2924/00014 , H01L2924/1306 , H01L2924/181 , H01L2924/014 , H01L2924/00015 , H01L2924/01046 , H01L2924/01028 , H01L2924/01029 , H01L2924/01024 , H01L2224/0231 , H01L2924/00012
Abstract: To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.
Abstract translation: 通过提高半导体芯片和接合线之间的耦合性能来提供具有提高的可靠性的半导体器件。 再分配层由从半导体基板侧连续形成的Cu膜，Ni膜和Pd膜构成。 将最上表面的Pd膜用作电极焊盘，并且由Cu制成的接合线耦合到Pd膜的上表面。 使得Pd膜的厚度小于Ni膜的厚度，并使Ni膜的厚度小于Cu膜的厚度。 Cu膜，Ni膜和Pd膜在平面图中具有相同的图案形状。
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公开(公告)号：US20140021618A1
公开(公告)日：2014-01-23
申请号：US13924938
申请日：2013-06-24
Applicant: Renesas Electronics Corporation
Inventor： Hisao SHIGIHARA , Hiromi SHIGIHARA , Akira YAJIMA , Hiroshi TSUKAMOTO
IPC: H01L23/498 , H01L21/48
CPC classification number: H01L23/53238 , H01L21/4885 , H01L23/293 , H01L23/3192 , H01L23/4952 , H01L23/49811 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/43 , H01L24/45 , H01L24/46 , H01L24/48 , H01L24/85 , H01L24/94 , H01L2224/02311 , H01L2224/02313 , H01L2224/02373 , H01L2224/02377 , H01L2224/02379 , H01L2224/0239 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/03474 , H01L2224/0361 , H01L2224/03914 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05084 , H01L2224/05147 , H01L2224/05155 , H01L2224/05171 , H01L2224/05548 , H01L2224/05552 , H01L2224/05569 , H01L2224/05644 , H01L2224/05664 , H01L2224/06135 , H01L2224/06138 , H01L2224/131 , H01L2224/13144 , H01L2224/16245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/48644 , H01L2224/48664 , H01L2224/48844 , H01L2224/48864 , H01L2224/85181 , H01L2224/94 , H01L2924/00 , H01L2924/00014 , H01L2924/1306 , H01L2924/181 , H01L2924/014 , H01L2924/00015 , H01L2924/01046 , H01L2924/01028 , H01L2924/01029 , H01L2924/01024 , H01L2224/0231 , H01L2924/00012
Abstract: To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.
Abstract translation: 通过提高半导体芯片和接合线之间的耦合性能来提供具有提高的可靠性的半导体器件。 再分配层由从半导体基板侧连续形成的Cu膜，Ni膜和Pd膜构成。 将最上表面的Pd膜用作电极焊盘，并且由Cu制成的接合线耦合到Pd膜的上表面。 使得Pd膜的厚度小于Ni膜的厚度，并使Ni膜的厚度小于Cu膜的厚度。 Cu膜，Ni膜和Pd膜在平面图中具有相同的图案形状。
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