公开(公告)号：US09196594B2

公开(公告)日：2015-11-24

申请号：US14337121

申请日：2014-07-21

Applicant: XINTEC INC.

Inventor： Chao-Yen Lin ,  Yi-Hang Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/525 ,  H01L29/06 ,  G06K9/00 ,  H05K1/18

CPC classification number: H01L24/05 ,  G06K9/0004 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/525 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L29/06 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/0801 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/3701 ,  H05K1/181 ,  H05K2201/09418 ,  H05K2201/09445 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

公开(公告)号：US09165890B2

公开(公告)日：2015-10-20

申请号：US13941854

申请日：2013-07-15

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shih-Chin Chen ,  Yi-Ming Chang ,  Chien-Hui Chen ,  Chia-Ming Cheng ,  Wei-Luen Suen ,  Chen-Han Chiang

IPC: H01L23/544 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/1416 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 设置在所述基板中的装置区域; 位于半导体衬底的第一表面上的电介质层; 位于所述电介质层中并电连接到所述器件区域的多个导电焊盘; 设置在所述半导体衬底中并且从所述第二表面朝向所述第一表面延伸的至少一个对准标记。

公开(公告)号：US20150287619A1

公开(公告)日：2015-10-08

申请号：US14676478

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: H01L21/67 ,  H01L21/78 ,  B26F3/00 ,  H01L21/683 ,  H01L21/30

CPC classification number: H01L21/67092 ,  B26D1/095 ,  B26D7/1863 ,  H01L21/6838 ,  Y10T83/0267 ,  Y10T225/10 ,  Y10T225/12 ,  Y10T225/364

Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body. The cap layer is pressed against by the bottom surface of the suction pad and sucked by the suction pad of the vacuum nozzle head after the vacuum pump begins to vacuum the air within the hollow vacuum pipe and the through hole. Then, the first cutter cuts into the interface between the substrate and the cap layer, and the cap lay is separated from the substrate by the suction force of the vacuum nozzle head and the lift force generated by the upward movement of the vacuum nozzle head.

Abstract translation: 本发明的一个实施例提供了一种分离装置，用于分离堆叠制品，例如具有感测功能的半导体芯片封装，包括基板和形成在基板上的盖层。 分离装置包括：真空喷嘴头，包括具有顶表面和底表面的吸盘，穿过吸垫的顶表面和底表面的通孔;以及将通孔连接到真空泵的中空真空管 ; 位于真空喷嘴头下方并基本上与吸盘对准的阶段; 连接到真空喷嘴头以将真空喷嘴头向上或向下提升的控制装置; 以及第一切割器，其包括连接到第一切割体的第一切割体和第一切割刀。 在真空泵开始真空吸入中空真空管和通孔中的空气之后，盖层被吸盘的底面压紧并被真空喷嘴头的吸盘吸入。 然后，第一切割器切入基板和盖层之间的界面，并且通过真空喷嘴头的吸力和由真空喷嘴头的向上运动产生的提升力将盖子与基板分离。

公开(公告)号：US20150284244A1

公开(公告)日：2015-10-08

申请号：US14676738

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: B81C1/00 ,  H01L21/683 ,  H01L23/00 ,  H01L27/146 ,  H01L21/78

CPC classification number: B81C1/00896 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/11 ,  H01L24/43 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/0231 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/05432 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for forming a chip package is provided. The method includes providing a substrate and a capping layer, wherein the substrate has a sensing device therein adjacent to a surface of the substrate. The capping layer is attached to the surface of the substrate by an adhesive layer, wherein the adhesive layer covers the sensing device. A dicing process is performed on the substrate, the adhesive layer, and the capping layer along a direction to form individual chip packages.

Abstract translation: 提供了一种形成芯片封装的方法。 该方法包括提供衬底和覆盖层，其中衬底在其中邻近衬底的表面具有感测装置。 封盖层通过粘合剂层附接到基底的表面，其中粘合剂层覆盖感测装置。 沿着形成单个芯片封装的方向在衬底，粘合剂层和覆盖层上进行切割工艺。

公开(公告)号：US09093450B2

公开(公告)日：2015-07-28

申请号：US14077877

申请日：2013-11-12

Applicant: XINTEC INC.

Inventor： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang

IPC: H01L21/50 ,  H01L25/00 ,  B81C1/00 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L25/50 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/0023 ,  B81C2203/0109 ,  B81C2203/0792 ,  H01L21/6835 ,  H01L24/94 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip.

Abstract translation: 芯片封装包括具有上表面和下表面的衬底，并且包括：至少第一接触焊盘; 设置在上表面上的非光学传感器芯片，其中所述非光学传感器芯片至少包括第二接触焊盘并具有第一长度; 设置在所述非光学传感器芯片上的保护盖，其中所述保护盖具有第二长度，所述第二长度的延伸方向基本上平行于所述第一长度的延伸方向，并且所述第二长度短于所述第一长度; 设置在所述保护盖上的IC芯片，其中所述IC芯片包括至少第三接触焊盘并具有第三长度，并且所述第三长度的延伸方向基本上与所述第一长度的延伸方向平行; 以及在基板，非光学传感器芯片和IC芯片之间形成电连接的接合线。

公开(公告)号：US20150206916A1

公开(公告)日：2015-07-23

申请号：US14595870

申请日：2015-01-13

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chien-Hung LIU

IPC: H01L27/146 ,  H01L31/0203

CPC classification number: H01L27/14632 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2224/11

Abstract: A manufacturing method of a semiconductor device includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A redistribution layer, an insulating layer, and a conductive structure are formed on a second surface of the wafer opposite to the first surface, such that a semiconductor element is formed. The semiconductor element is diced from the insulating layer to the carrier, such that the semiconductor element forms at least one sub-semiconductor element. UV light is used to irradiate the sub-semiconductor element, such that adhesion of the temporary bonding layer is eliminated. The carrier of the sub-semiconductor element is removed.

Abstract translation: 半导体器件的制造方法包括以下步骤。 临时粘合层用于将载体粘附到晶片的第一表面。 在与第一表面相对的晶片的第二表面上形成再分布层，绝缘层和导电结构，从而形成半导体元件。 半导体元件从绝缘层切割到载体，使得半导体元件形成至少一个子半导体元件。 UV光用于照射次半导体元件，从而消除了临时粘合层的粘附。 子半导体元件的载体被去除。

公开(公告)号：US20150137341A1

公开(公告)日：2015-05-21

申请号：US14540460

申请日：2014-11-13

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/28

CPC classification number: H01L23/5386 ,  B81B7/0064 ,  B81B2207/096 ,  H01L21/561 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/29011 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48471 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package including a first substrate having a first surface and a second surface opposite thereto is provided. The first substrate has a micro-electric element and a plurality of conducting pads adjacent to the first surface. The first substrate has a plurality of openings respectively exposing a portion of each conducting pad. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conducting pads.

Abstract translation: 提供了包括具有第一表面和与其相对的第二表面的第一基板的芯片封装。 第一基板具有微电元件和与第一表面相邻的多个导电垫。 第一基板具有分别暴露每个导电垫的一部分的多个开口。 第二基板设置在第一表面上。 封装层设置在第一表面上并覆盖第二基板。 再分配层设置在第二表面上并延伸到开口中以电连接导电垫。

公开(公告)号：US20150132949A1

公开(公告)日：2015-05-14

申请号：US14592818

申请日：2015-01-08

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Po-Han LEE

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/481 ,  H01L21/76897 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/20 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Abstract translation: 提供了芯片封装及其制造方法。 芯片封装包括具有第一表面和相对的第二表面的半导体衬底。 间隔件设置在半导体衬底的第二表面下方，并且覆盖板设置在间隔件下方。 形成与半导体衬底的侧壁相邻的凹部，从半导体衬底的第一表面延伸到至少间隔件。 然后，保护层设置在半导体衬底的第一表面和凹部中。

公开(公告)号：US09013043B2

公开(公告)日：2015-04-21

申请号：US13667811

申请日：2012-11-02

Applicant: Xintec Inc.

Inventor： Hung-Chang Chen

IPC: H01L23/488 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/488 ,  H01L24/02 ,  H01L27/14618

Abstract: A semiconductor element includes: a transparent substrate; a stack structure formed on the transparent substrate and having a metal oxide layer partially exposed through sidewalls of the stack structure; a plurality of leads spacingly formed on the stack structure and extending to the sidewalls of the stack structure; an insulating film covering the exposed portions of the metal oxide layer; a metal film formed on the leads; and a solder mask layer disposed on the metal film, the stack structure and the insulating film. As such, the insulating film prevents short circuits from occurring between adjacent leads so as to improve the product yield.

Abstract translation: 半导体元件包括：透明基板; 形成在所述透明基板上并具有通过所述堆叠结构的侧壁部分露出的金属氧化物层的堆叠结构; 多个引线间隔地形成在堆叠结构上并延伸到堆叠结构的侧壁; 覆盖金属氧化物层的暴露部分的绝缘膜; 在引线上形成金属膜; 以及设置在金属膜，堆叠结构和绝缘膜上的焊料掩模层。 因此，绝缘膜防止相邻导线之间发生短路，从而提高产品产量。

公开(公告)号：US09006896B2

公开(公告)日：2015-04-14

申请号：US13887917

申请日：2013-05-06

Applicant: Xintec Inc.

Inventor： Yu-Lung Huang ,  Tsang-Yu Liu ,  Shu-Ming Chang

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/78 ,  B81B7/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/49811 ,  B81B7/007 ,  B81B2207/092 ,  B81B2207/095 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 设置在所述半导体衬底的第一表面上的电介质层; 导电焊盘结构，其位于所述电介质层中并电连接到所述器件区域，其中所述导电焊盘结构包括多个导电焊盘层的堆叠结构; 支撑层，设置在所述导电焊盘结构的顶表面上; 以及设置在半导体衬底的第二表面上的保护层。