公开(公告)号：US11696396B2

公开(公告)日：2023-07-04

申请号：US17585363

申请日：2022-01-26

Applicant: JF MICROTECHNOLOGY SDN. BHD

Inventor： Wei Kuong Foong ,  Kok Sing Goh ,  Shamal Mundiyath ,  Eng Kiat Lee ,  Grace Ann Nee Yee

IPC: H05K1/02

CPC classification number: H05K1/0296 ,  H05K1/0268 ,  H05K1/0283 ,  H05K2201/1078 ,  H05K2201/1084 ,  H05K2201/10704 ,  H05K2201/10795

Abstract: An electrical contact assembly that uses an elastomer strip for each row of individual contacts. Each contact comprises a rigid bottom pin and a flexible top pin with a pair of arms which extend over and slide along sloped surfaces of the bottom contact. The elastomer strip is located between rows of the bottom and top pins. A bottom socket housing is provided with grooves which receive each elastomer strip. A row of top pins is then placed over each elastomer strip, and through ducts in the bottom socket housing. Bottom pins are then snapped into place in between the pair of arms.

公开(公告)号：US20180331081A1

公开(公告)日：2018-11-15

申请号：US15777458

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Wee Hoe ,  Khang Choong Yong ,  Ping Ping Ooi

IPC: H01L25/16 ,  H01L25/18 ,  H05K1/18 ,  H01L23/538 ,  H01L25/00 ,  H05K3/30 ,  H05K1/14

CPC classification number: H01L25/16 ,  H01L23/48 ,  H01L23/5386 ,  H01L25/065 ,  H01L25/18 ,  H01L25/50 ,  H01L2924/1432 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19042 ,  H01L2924/19106 ,  H05K1/144 ,  H05K1/147 ,  H05K1/181 ,  H05K3/303 ,  H05K2201/048 ,  H05K2201/055 ,  H05K2201/1003 ,  H05K2201/10098 ,  H05K2201/10151 ,  H05K2201/10159 ,  H05K2201/10356 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180242447A1

公开(公告)日：2018-08-23

申请号：US15961098

申请日：2018-04-24

Applicant: ALCATEL-LUCENT CANADA INC.

Inventor： James M. SCHRIEL ,  Alex L. CHAN ,  Paul J. BROWN

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K1/0296 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/181 ,  H05K3/0005 ,  H05K2201/10704 ,  H05K2201/10712 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.

公开(公告)号：US20180047695A1

公开(公告)日：2018-02-15

申请号：US15797124

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Yoshikazu SHIMOTE ,  Shinji BABA ,  Toshihiro IWASAKI ,  Kazuyuki NAKAGAWA

IPC: H01L23/00 ,  H01L23/50 ,  H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H05K3/34 ,  H05K3/28

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/562 ,  H01L23/564 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16055 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1713 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/85 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/2064 ,  H01L2924/351 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/09427 ,  H05K2201/10704 ,  H05K2201/10977 ,  H05K2203/0465 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/45099 ,  H01L2924/207

Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

公开(公告)号：US09793634B2

公开(公告)日：2017-10-17

申请号：US15060728

申请日：2016-03-04

Applicant: International Business Machines Corporation

Inventor： Na Fan ,  Jun Hu ,  Sen Xiong Huang ,  YongDong Shi ,  XiYuan Yin

IPC: H01R13/415 ,  H01R13/11 ,  H01R43/04 ,  H01R12/71

CPC classification number: H01R13/11 ,  H01R12/57 ,  H01R12/716 ,  H01R43/04 ,  H01R43/205 ,  H05K1/184 ,  H05K3/3447 ,  H05K7/1069 ,  H05K2201/10303 ,  H05K2201/10704 ,  H05K2201/1078 ,  H05K2201/10803

Abstract: A socket housing and contact assembly process includes forming the solder ball contact region after initial installation of a set of contacts into the housing. The contact regions of the set of contacts pass through corresponding contact cavities to extend beyond the housing and the contact regions are formed over at equal angles for solder ball placement.

公开(公告)号：US09013869B2

公开(公告)日：2015-04-21

申请号：US14145584

申请日：2013-12-31

Applicant: Apple Inc.

Inventor： Brett W. Degner ,  Gregory Tice

IPC: H05K7/20 ,  G06F1/20 ,  H01L23/40 ,  H05K3/30 ,  H05K7/12 ,  H01L23/473 ,  H01L23/427

CPC classification number: G06F1/20 ,  H01L23/4006 ,  H01L23/427 ,  H01L23/473 ,  H01L2924/0002 ,  H05K3/301 ,  H05K7/12 ,  H05K7/20 ,  H05K7/20254 ,  H05K2201/064 ,  H05K2201/10265 ,  H05K2201/10325 ,  H05K2201/10393 ,  H05K2201/10704 ,  H05K2203/0278 ,  Y10T29/49124 ,  Y10T29/49826 ,  Y10T29/53113 ,  H01L2924/00

Abstract: A low profile heat removal system suitable for removing excess heat generated by an integrated circuit operating in a compact computing environment is disclosed.

Abstract translation: 公开了一种适用于去除在紧凑的计算环境中工作的集成电路产生的多余热量的低轮廓散热系统。

公开(公告)号：US08659909B2

公开(公告)日：2014-02-25

申请号：US11588682

申请日：2006-10-27

Applicant: Damion Searls ,  Edward Osburn

Inventor： Damion Searls ,  Edward Osburn

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H01L23/49844 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1531 ,  H01L2924/19106 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/1006 ,  H05K2201/10166 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10704 ,  Y10T29/4913 ,  Y10T29/49147 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

Abstract translation: 在一个实施例中，本发明包括将半导体器件安装到电路板的第一侧的方法; 以及将至少一个电压调节器装置安装到所述电路板的第二侧，所述第二侧与所述第一侧相对。 电压调节器装置可以是输出滤波器，电感器，电容器等。 在某些实施例中，器件可以位于半导体器件的正下方。

公开(公告)号：US20130283608A1

公开(公告)日：2013-10-31

申请号：US13926069

申请日：2013-06-25

Applicant: Interplex Industries, Inc.

Inventor： Jack Seidler

IPC: H05K3/00

CPC classification number: H05K3/00 ,  B23K35/0244 ,  H01R12/57 ,  H01R12/707 ,  H01R43/0235 ,  H05K3/3426 ,  H05K3/3478 ,  H05K3/3489 ,  H05K2201/0311 ,  H05K2201/10704 ,  H05K2201/10795 ,  H05K2201/1084 ,  H05K2201/10924 ,  H05K2201/10984 ,  H05K2203/0405 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49147

Abstract: A method of fixing reflowable elements on electrical contacts. The method includes providing a strip having a number of electrical contacts, each contact including a contact body and a tail portion extending away from the contact body. The tail portions of the contacts are then disposed adjacent an elongate reflowable member. The elongate reflowable member is pushed onto the tail portions of the plurality of contacts. Subsequently, the elongate reflowable member is cut into a plurality of separate reflowable elements, each reflowable element corresponding to one of the tail portions. The electrical contacts with the reflowable element attached thereto are separated from the strip.

Abstract translation: 将可回流元件固定在电触点上的方法。 该方法包括提供具有多个电触点的条带，每个触点包括接触体和远离接触体延伸的尾部。 然后将触头的尾部设置在细长的可回流构件附近。 细长的可回流构件被推到多个触点的尾部。 随后，细长可回流构件被切割成多个单独的可回流元件，每个可回流元件对应于尾部中的一个。 与附接到其上的可回流元件的电接触与条分离。

公开(公告)号：US20120222891A1

公开(公告)日：2012-09-06

申请号：US13508974

申请日：2010-10-20

Applicant: Hisashi Ishida

Inventor： Hisashi Ishida

IPC: H05K1/03 ,  H05K3/10 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16

CPC classification number: H05K1/0236 ,  H05K1/0233 ,  H05K1/141 ,  H05K2201/09727 ,  H05K2201/10265 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y10T29/49155

Abstract: A first interconnect substrate includes a first conductor pattern. A second interconnect substrate includes a second conductor pattern. At least a portion of the second conductor pattern is formed in a region opposite the first conductor pattern. At least either the first conductor pattern or the second conductor pattern has a repeated structure. The first conductor pattern and the second conductor pattern constitute at least a portion of an electromagnetic band gap (EBG) structure.

Abstract translation: 第一互连基板包括第一导体图案。 第二互连基板包括第二导体图案。 第二导体图案的至少一部分形成在与第一导体图案相对的区域中。 第一导体图案或第二导体图案中的至少一个具有重复的结构。 第一导体图案和第二导体图案构成电磁带隙（EBG）结构的至少一部分。

公开(公告)号：US20120043653A1

公开(公告)日：2012-02-23

申请号：US12926626

申请日：2010-11-30

Applicant: Heung Jae Oh ,  Jin Won Choi ,  Ki Taek Lee

Inventor： Heung Jae Oh ,  Jin Won Choi ,  Ki Taek Lee

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H05K3/4015 ,  H01L2924/15312 ,  H05K3/3426 ,  H05K2201/10318 ,  H05K2201/10704

Abstract: Disclosed herein is a lead pin for a package substrate. The lead pin for the package substrate according to the exemplary embodiment of the present invention includes a head part having one surface opposite to the package substrate and the other surface that is an opposite side to the one surface; and a connection pin having a pin shape bonded to the other surface of the head part, wherein the head part has a concave depression part toward the package substrate.

Abstract translation: 这里公开了一种用于封装衬底的引脚。 根据本发明的示例性实施例的封装基板的引脚包括具有与封装基板相对的一个表面和与该表面相对的另一个表面的头部; 以及具有与所述头部的另一个表面接合的销形状的连接销，其中，所述头部具有朝向所述封装基板的凹陷部。