公开(公告)号：US06623651B2

公开(公告)日：2003-09-23

申请号：US09815364

申请日：2001-03-22

Applicant: Bharat Patel ,  Jay D. Baker ,  Mohan Paruchuri

Inventor： Bharat Patel ,  Jay D. Baker ,  Mohan Paruchuri

IPC: H01B1300

CPC classification number: H05K3/44 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4647 ,  H05K3/4652 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536

Abstract: A method 10 for making a multi-layer electronic circuit board 98 having at least one electrically conductive protuberance 15 which forms a “via” and which traverses through the various layers of the electric circuit board 98, and further having at least one interconnection portion 102 which supports a wide variety of components and interconnection assemblies.

Abstract translation: 一种用于制造多层电子电路板98的方法10，该多层电子电路板98具有形成“通孔”的至少一个导电突起15，并穿过电路板98的各个层，并且还具有至少一个互连部分102 其支持各种组件和互连组件。

公开(公告)号：US06613986B1

公开(公告)日：2003-09-02

申请号：US09787321

申请日：2001-05-17

Applicant: Naohiro Hirose ,  Honjin En

Inventor： Naohiro Hirose ,  Honjin En

IPC: H05K103

CPC classification number: H01L29/40 ,  H01L21/4763 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/03 ,  H05K3/064 ,  H05K3/244 ,  H05K3/382 ,  H05K3/403 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09681 ,  H05K2203/1178

Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 &mgr;m. The reason is as follows. If the diameter of the mesh hole is less than 75 &mgr;m, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 &mgr;m, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 &mgr;m. The reason is as follows. If the distance is less than 100 &mgr;m, the solid layer cannot function. If the distance exceeds 2000 &mgr;m, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

公开(公告)号：US20030121146A1

公开(公告)日：2003-07-03

申请号：US10239731

申请日：2002-11-14

Inventor： Walter Schmidt

IPC: H05K003/02 ,  H05K003/10

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer are and a prefabricated product are placed between a support and a perforation die. The prefabricated product is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die, perforation tips of the perforation die forming microvias for contacting the structures. A surface of the dielectric layer or the prefabricated product is configured or coated to in a manner that the prefabricated product and the dielectric layer stick to each other after the pressure has been applied.

Abstract translation: 根据本发明，将微穿孔（PMP）工艺步骤与层压工艺组合。 为此，介电层和预制产品被放置在支撑件和穿孔模具之间。 预制产品被形成由微孔接触的结构的导电层部分覆盖。 在穿孔模具上施加压力，穿孔模具的穿孔尖端形成用于接触结构的微孔。 在施加压力之后，电介质层或预制产品的表面被构造或涂覆成使得预制产品和电介质层彼此粘合。

公开(公告)号：US20030113443A1

公开(公告)日：2003-06-19

申请号：US10352483

申请日：2003-01-28

Applicant: Motorola, Inc.

Inventor： Augus Kingon ,  Gregory J. Dunn ,  Stephen Streiffer ,  Kevin Cheek ,  Min-Xian Zhang ,  Jon-Paul Maria ,  Jovica Savic

IPC: B05D005/12 ,  B05D001/36

CPC classification number: H05K1/162 ,  H01G4/1218 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/121 ,  Y10T29/417

Abstract: A dielectric film is formed on a free-standing conductive metal layer to form a multi-layer foil comprising a conductive metal layer, a barrier layer and a dielectric oxide layer. Such multi-layer foils are mechanically flexible, and useful for the manufacture of capacitors. Examples of barrier layers include NinullP or NinullCr alloys. After a second layer of conductive metal is deposited on a dielectric oxide surface opposing the first conductive metal layer, the resulting capacitor foil is processed into a capacitor. The resulting capacitor is a surface mounted capacitor or is formed as a integrated or embedded capacitor within a circuit board.

公开(公告)号：US20030043556A1

公开(公告)日：2003-03-06

申请号：US10232661

申请日：2002-09-03

Applicant: HITACHI CABLE, LTD.

Inventor： Hiroshi Sugimoto ,  Tatsuya Ohtaka ,  Shigeharu Takahagi

IPC: H05K007/02 ,  H05K007/06 ,  H05K007/08

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09527 ,  H01L2224/05599

Abstract: A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a second conductor layer that is provided with a conductor pattern connected through a via to a ground wiring, for supplying a power supply of ground potential to the semiconductor chip; and a third conductor layer that is provided with a power supply terminal connected through a via to a power supply wiring for supplying an operation power supply of a potential other than the ground potential to the semiconductor chip, a signal terminal connected through a via to a signal wiring for transmitting an electric signal, and a ground terminal connected through a via to the conductor pattern in the second conductor layer.

Abstract translation: 具有微带结构的布线板具有：第一导体层，其在其外部端子（接合焊盘）中设置有与半导体芯片连接的导体布线; 第二导体层，其设置有通过通孔连接到接地布线的导体图案，用于向半导体芯片提供接地电位; 以及第三导体层，其具有通过通孔连接到电源布线的电源端子，用于向半导体芯片提供除了地电位以外的电位的操作电源，通过通孔连接到 用于发送电信号的信号线路，以及通过通孔连接到第二导体层中的导体图案的接地端子。

公开(公告)号：US20030034174A1

公开(公告)日：2003-02-20

申请号：US10198341

申请日：2002-07-18

Inventor： Zhong-You Shi ,  Delin Li ,  Richard McMillan

IPC: H05K003/20 ,  H01R012/04

CPC classification number: H05K3/429 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method 10, 110 for making multi-layer circuit boards having metallized apertures 38, 40, 130, 132 which may be selectively and electrically grounded and having at least one formed air-bridge 92, 178.

Abstract translation: 一种用于制造具有金属化孔38,40,130,132的多层电路板的方法10,110，其可以选择性地和电接地并且具有至少一个形成的空气桥92,178。

公开(公告)号：US20030024719A1

公开(公告)日：2003-02-06

申请号：US10263006

申请日：2002-10-02

Applicant: Motorola, Inc.

Inventor： Jeffrey A. Underwood ,  John K. Arledge ,  Thomas J. Swirbel ,  Joaquin Barreto

IPC: H05K009/00

CPC classification number: H05K1/0218 ,  H01L2223/6622 ,  H05K1/0221 ,  H05K1/0222 ,  H05K1/113 ,  H05K3/4644 ,  H05K9/0039 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09809 ,  H05K2201/09972 ,  H05K2201/09981 ,  H05K2201/10553 ,  H05K2201/10969 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: Methods and apparatus for forming a metal shield on a printed circuit board (10) include a layer of dielectric material (23) one or more printed circuits (21) on the layer of dielectric material (23), a layer of metal (27) on the layer of dielectric material (23), a metal-clad trench or opening surrounding the printed circuit (44) and electrically connected to the layer of metal(27), a solder pad (24) on the layer of dielectric material (23), a microvia (25) through the solder pad (24) and the layer of dielectric material (23), and electrical components (11) soldered to the solder pads (24) and to the printed circuit (21).

Abstract translation: 在印刷电路板（10）上形成金属屏蔽的方法和装置包括介电材料层（23），介电材料层（23）上的一个或多个印刷电路（21），一层金属（27） 在电介质材料层（23）上，围绕印刷电路（44）并电连接到金属层（27）的金属包覆沟槽或开口，介电材料层（23）上的焊盘（24） ），通过焊盘（24）和电介质材料层（23）的微孔（25）以及焊接到焊盘（24）和印刷电路（21）的电气部件（11）。

公开(公告)号：US20030014728A1

公开(公告)日：2003-01-16

申请号：US10243432

申请日：2002-09-13

Inventor： Ian P. Shaeffer ,  Everett Basham

IPC: G06F017/50 ,  H03K017/693

CPC classification number: H05K7/1061 ,  H01R12/52 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10378

Abstract: A system and method is described for providing a robust mechanical and electrical connection between two or more circuit boards which may be employed for diagnostic purposes and/or for permanent connections. A spacer block, connection block, or pedestal, preferably made of PCB type material is preferably disposed between two PCBs. The pedestal is preferably dimensioned to space the two PCBs far enough apart that the surface mount components on two boards connected employing the inventive pedestal do not interfere with one another. The pedestal preferably provides for ample signal density and signal quality because of the block thickness and availability of insulation within the pedestal.

公开(公告)号：US20030010440A1

公开(公告)日：2003-01-16

申请号：US10217616

申请日：2002-08-12

Inventor： Anilkumar C. Bhatt ,  Stephen J. Fuerniss ,  Joan Congelosi ,  Roy H. Magnuson ,  Voya R. Markovich

IPC: B32B031/00 ,  B32B031/26

CPC classification number: B32B7/04 ,  B32B27/26 ,  B32B27/32 ,  B32B2250/40 ,  B32B2305/72 ,  H05K3/0023 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/09509 ,  H05K2201/09536 ,  Y10S428/901 ,  Y10T428/24273 ,  Y10T428/28 ,  Y10T428/31511

Abstract: A dielectric structure, and an associated method of fabrication, wherein two fully cured photoimageable dielectric (PID) layers of the structure are nonadhesively interfaced by a partially cured PID layer. The partially cured PID layer includes a power plane sandwiched between a first partially cured PID sheet and a second partially cured PID sheet. The partially cured PID layer be formed either in isolation, or by successively forming upon one of the fully cured PID layers: the first partially cured PID sheet, the power plane, and the second partially cured PID sheet. The first partially cured PID sheet and the second partially cured PID sheet is the result of partially curing, by radiative exposure, a first uncured PID sheet and a second uncured PID sheet, respectively. The fully cured PID layers each include an internal power plane, a plated via having a blind end conductively coupled to the internal power plane, and a plated via passing through the fully cured PID layer. The dielectric structure may further include a first PID film partially cured by radiation and nonadhesively coupled to one of the fully cured PID layers. The dielectric structure may further include a second PID film partially cured by radiation and nonadhesively coupled to the other fully cured PID layer. The partially cured PID material of the dielectric structure may be fully cured by pressurization and/or elevated temperature.

Abstract translation: 电介质结构和相关联的制造方法，其中该结构的两个完全固化的可光成像电介质（PID）层通过部分固化的PID层非粘性地接合。 部分固化的PID层包括夹在第一部分固化的PID片和第二部分固化的PID片之间的动力平面。 部分固化的PID层被隔离形成，或者通过连续地形成在完全固化的PID层之一上：第一部分固化的PID片，动力平面和第二部分固化的PID片。 第一部分固化的PID片和第二部分固化的PID片分别是通过辐射曝光部分固化，第一未固化的PID片和第二未固化的PID片的结果。 完全固化的PID层各自包括内部电源平面，具有导电耦合到内部电源平面的盲端的电镀通孔以及穿过完全固化的PID层的电镀通孔。 电介质结构可以进一步包括通过辐射部分固化并且非粘性地耦合到完全固化的PID层之一的第一PID膜。 电介质结构可以进一步包括通过辐射部分地固化并且非粘性地耦合到另一完全固化的PID层的第二PID膜。 电介质结构的部分固化的PID材料可以通过加压和/或升高的温度完全固化。

公开(公告)号：US06495239B1

公开(公告)日：2002-12-17

申请号：US09458291

申请日：1999-12-10

Applicant: Anilkumar C. Bhatt ,  Stephen J. Fuerniss ,  Roy H. Magnuson ,  Voya R. Markovich

Inventor： Anilkumar C. Bhatt ,  Stephen J. Fuerniss ,  Roy H. Magnuson ,  Voya R. Markovich

IPC: B32B310

CPC classification number: B32B7/04 ,  B32B27/26 ,  B32B27/32 ,  B32B2250/40 ,  B32B2305/72 ,  H05K3/0023 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/09509 ,  H05K2201/09536 ,  Y10S428/901 ,  Y10T428/24273 ,  Y10T428/28 ,  Y10T428/31511

Abstract: A dielectric structure, wherein two fully cured photoimageable dielectric (PID) layers of the structure are nonadhesively interfaced by a partially cured PID layer. The partially cured PID layer includes a power plane sandwiched between a first partially cured PID sheet and a second partially cured PID sheet. The fully cured PID layers each include an internal power plane, a plated via having a blind end conductively coupled to the internal power plane, and a plated via passing through the fully cured PID layer. The dielectric structure may further include a first PID film partially cured and nonadhesively coupled to one of the fully cured PID layers. The dialectric structure may further include a second PID film partially cured and nonadhesively coupled to the other fully cured PID layer.

Abstract translation: 一种电介质结构，其中该结构的两个完全固化的可光成像电介质（PID）层通过部分固化的PID层非粘性地接合。 部分固化的PID层包括夹在第一部分固化的PID片和第二部分固化的PID片之间的动力平面。 完全固化的PID层各自包括内部电源平面，具有导电耦合到内部电源平面的盲端的电镀通孔以及穿过完全固化的PID层的电镀通孔。 电介质结构还可以包括部分固化并非粘性地耦合到完全固化的PID层之一的第一PID膜。 所述方程式结构还可以包括部分固化并非粘性地耦合到另一完全固化的PID层的第二PID膜。