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    Plating Process and Structure
    22.
    发明申请
    Plating Process and Structure 有权
    电镀工艺与结构

    公开(公告)号：US20130119382A1

    公开(公告)日：2013-05-16

    申请号：US13297845

    申请日：2011-11-16

    Applicant: Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

    Inventor： Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

    IPC: H01L23/544 ,  H01L21/28

    CPC classification number: H01L22/32

    Abstract: A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed.

    Abstract translation: 提供了一种用于电镀触点的系统和方法。 一个实施例包括在触点和测试垫上形成保护层，然后在触头上选择性地去除保护层，而不需要在测试垫上移除保护层。 在保护层仍在测试焊盘上的情况下，可以将导电层电镀到触点上，而不将其覆盖在测试焊盘上。 接触电镀后，触点上的保护层可以被去除。

    Ultra-shallow junctions using atomic-layer doping
    26.
    发明授权
    Ultra-shallow junctions using atomic-layer doping 有权
    使用原子层掺杂的超浅结

    公开(公告)号：US08361895B2

    公开(公告)日：2013-01-29

    申请号：US12211464

    申请日：2008-09-16

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L21/22 ,  H01L21/38

    CPC classification number: H01L29/66636 ,  H01L21/2254 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/49 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    Abstract: A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing sides of the gate stack. The substrate may be recessed prior to forming the atomic layer and the recess may be filled by an epitaxial process. The depositing, annealing, and, if used, epitaxial growth may be repeated a plurality of times to achieve the desired junctions. Source/drain regions are also provided on opposing sides of the gate stack.

    Abstract translation: 提供半导体器件和制造方法。 基板上形成有栅叠层。 通过沉积掺杂剂的原子层并执行退火来形成超浅结，以将掺杂剂扩散到栅叠层的相对侧上的衬底中。 衬底可以在形成原子层之前被凹入，并且凹槽可以通过外延工艺填充。 可以重复沉积，退火和（如果使用）外延生长以实现所需的结。 源极/漏极区域也设置在栅极堆叠的相对侧上。

    High voltage gain power converter
    29.
    发明授权
    High voltage gain power converter 失效
    高压增益电源转换器

    公开(公告)号：US08199540B2

    公开(公告)日：2012-06-12

    申请号：US12683412

    申请日：2010-01-06

    Applicant: Ching-Shan Leu ,  Jing-Cheng Lin ,  Shun-Yuan Wu

    Inventor： Ching-Shan Leu ,  Jing-Cheng Lin ,  Shun-Yuan Wu

    IPC: H02J1/10 ,  H02J3/14 ,  H02M7/08 ,  H02M7/10

    CPC classification number: H02M3/155 ,  H02M3/158 ,  H02M2001/009 ,  Y10T307/406

    Abstract: A high voltage gain power converter includes: a main switch element; an assistant switch element; a first inductive element, a first switch element, and a first capacitive element; and a second inductive element, a second switch element, and a second capacitive element. The first inductive element is connected between an input node and first switch element. The first capacitive element, connected between the first switch element and ground, provides a first boost output voltage. The second inductive element is connected between the main switch element and first capacitive element. The second switch element is connected to a common node of the second inductive element and main switch element. The second capacitive element, connecting the second switch element to a first node, provides a second boost output voltage. The assistant switch element is connected between the first inductive element and common node of the second inductive element and main switch element.

    Abstract translation: 高压增益功率转换器包括：主开关元件; 辅助开关元件; 第一电感元件，第一开关元件和第一电容元件; 以及第二感应元件，第二开关元件和第二电容元件。 第一电感元件连接在输入节点和第一开关元件之间。 连接在第一开关元件和地之间的第一电容元件提供第一升压输出电压。 第二电感元件连接在主开关元件和第一电容元件之间。 第二开关元件连接到第二电感元件和主开关元件的公共节点。 将第二开关元件连接到第一节点的第二电容元件提供第二升压输出电压。 辅助开关元件连接在第二电感元件和主开关元件的第一电感元件和公共节点之间。

    Multiple-Gate Transistors with Reverse T-Shaped Fins
    30.
    发明申请
    Multiple-Gate Transistors with Reverse T-Shaped Fins 有权
    具有反向T形鳍的多栅极晶体管

    公开(公告)号：US20120058628A1

    公开(公告)日：2012-03-08

    申请号：US13294526

    申请日：2011-11-11

    Applicant: Li-Shyue Lai ,  Jing-Cheng Lin

    Inventor： Li-Shyue Lai ,  Jing-Cheng Lin

    IPC: H01L21/20

    CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

    Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

    Abstract translation: 形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。 外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。 水平板的底部接触半导体衬底。 该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。

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