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公开(公告)号:US20110248409A1
公开(公告)日:2011-10-13
申请号:US13168351
申请日:2011-06-24
申请人: Ku-Feng Yang , Weng-Jin WU , Wen-Chih Chiou , Chen-Hua Yu
发明人: Ku-Feng Yang , Weng-Jin WU , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号: H01L23/48
CPC分类号: H01L21/486 , H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/13009 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14181 , H01L2224/16146 , H01L2224/32145 , H01L2224/73203 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/01019 , H01L2224/11
摘要: A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer.
摘要翻译: 公开了一种用于堆叠半导体管芯的系统和方法。 优选实施例包括形成通过晶片的穿硅通孔,保护晶片的边缘边缘,然后去除未受保护的部分,使得边缘边缘的厚度大于薄的晶片。 该厚度有助于脆弱的晶片在进一步的运输和工艺步骤中保持生存。 然后优选在从晶片分离单个模具期间移除边缘。
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32.
公开(公告)号:US20110189837A1
公开(公告)日:2011-08-04
申请号:US12972184
申请日:2010-12-17
申请人: Chen-Hua Yu , Chia-Lin Yu , Ding-Yuan Chen , Wen-Chih Chiou
发明人: Chen-Hua Yu , Chia-Lin Yu , Ding-Yuan Chen , Wen-Chih Chiou
IPC分类号: H01L21/20
CPC分类号: H01L21/0237 , H01L21/02458 , H01L21/0254 , H01L21/02573 , H01L21/02617 , H01L21/02664
摘要: A method of forming a semiconductor structure includes providing a substrate; forming a buffer/nucleation layer over the substrate; forming a group-III nitride (III-nitride) layer over the buffer/nucleation layer; and subjecting the III-nitride layer to a nitridation. The step of forming the III-nitride layer comprises metal organic chemical vapor deposition.
摘要翻译: 形成半导体结构的方法包括提供基板; 在衬底上形成缓冲/成核层; 在缓冲/成核层上形成III族氮化物(III族氮化物)层; 并对该III族氮化物层进行氮化。 形成III族氮化物层的步骤包括金属有机化学气相沉积。
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公开(公告)号:US07972969B2
公开(公告)日:2011-07-05
申请号:US12043714
申请日:2008-03-06
申请人: Ku-Feng Yang , Wen-Chih Chiou , Weng-Jin Wu , Kewei Zuo
发明人: Ku-Feng Yang , Wen-Chih Chiou , Weng-Jin Wu , Kewei Zuo
IPC分类号: H01L21/302 , H01L21/461
CPC分类号: H01L21/67253 , H01L21/30604 , H01L21/6708 , H01L22/12 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要: A method is provided for controlling substrate thickness. At least one etchant is dispensed from at least one dispenser to a plurality of different locations on a surface of a spinning substrate to perform etching. A thickness of the spinning substrate is monitored at the plurality of locations, so that the thickness of the substrate is monitored at each individual location while dispensing the etchant at that location. A respective amount of etching performed at each individual location is controlled, based on the respective monitored thickness at that location.
摘要翻译: 提供了一种控制基板厚度的方法。 至少一种蚀刻剂从纺丝衬底的表面从至少一个分配器分配到多个不同位置以进行蚀刻。 在多个位置监测纺丝衬底的厚度,从而在每个单独位置监测衬底的厚度,同时在该位置分配蚀刻剂。 基于在该位置处的相应监视的厚度来控制在每个单独位置执行的相应的蚀刻量。
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公开(公告)号:US07956448B2
公开(公告)日:2011-06-07
申请号:US12878060
申请日:2010-09-09
申请人: Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Jean Wang
发明人: Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Jean Wang
IPC分类号: H01L23/06
CPC分类号: H01L21/76898 , H01L23/3114 , H01L23/3185 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/91 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/08145 , H01L2224/13009 , H01L2224/13013 , H01L2224/13014 , H01L2224/13025 , H01L2224/14051 , H01L2224/14135 , H01L2224/14155 , H01L2224/14179 , H01L2224/17517 , H01L2224/29011 , H01L2224/29013 , H01L2224/29035 , H01L2224/29075 , H01L2224/29116 , H01L2224/29124 , H01L2224/29147 , H01L2224/29169 , H01L2224/29184 , H01L2224/29186 , H01L2224/3003 , H01L2224/30155 , H01L2224/73103 , H01L2224/73203 , H01L2224/80895 , H01L2224/80896 , H01L2224/81193 , H01L2224/83193 , H01L2224/9202 , H01L2225/06517 , H01L2225/06541 , H01L2225/06582 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/12041 , H01L2924/14 , Y10S438/926 , H01L2924/00 , H01L2924/053 , H01L2924/049 , H01L2924/00014 , H01L2924/00012
摘要: A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure.
摘要翻译: 层叠结构包括结合到第二基板的第一基板,使得第一基板的第一焊盘结构接触第二基板的第二焊盘结构。 晶体管栅极形成在第二衬底上,并且第一导电结构延伸穿过第二衬底并且具有与第二衬底的顶表面基本平坦的顶表面。 在晶体管栅极上设置层间绝缘层(ILD)层,钝化层设置在ILD层之上,并且包括与第二导电结构电接触的第二焊盘结构。 ILD层包括延伸穿过ILD层并与晶体管栅极电接触的至少一个接触结构。 第二导电结构设置在ILD层中并且至少部分地设置在第一导电结构的表面上。
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公开(公告)号:US07812459B2
公开(公告)日:2010-10-12
申请号:US11641324
申请日:2006-12-19
申请人: Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Hung-Jung Tu , Ku-Feng Yang
发明人: Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Hung-Jung Tu , Ku-Feng Yang
IPC分类号: H01L23/48
CPC分类号: H01L21/8221 , H01L21/76898 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05157 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05568 , H01L2224/05573 , H01L2224/05609 , H01L2224/05616 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , Y10S148/164 , H01L2924/00014 , H01L2924/0105 , H01L2924/01079 , H01L2924/013
摘要: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.
摘要翻译: 半导体结构包括第一裸片,其包括第一衬底和第一衬底上的第一焊盘,第二裸片,具有与第一表面相对的第一表面和第二表面,其中第二裸片堆叠在第一裸片上, 层,其具有在第二管芯的侧壁上的垂直部分,以及在第一管芯上延伸的水平部分。
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公开(公告)号:US20100244284A1
公开(公告)日:2010-09-30
申请号:US12731281
申请日:2010-03-25
申请人: Ku-Feng YANG , Weng-Jin WU , Wen-Chih CHIOU , Tsung-Ding WANG
发明人: Ku-Feng YANG , Weng-Jin WU , Wen-Chih CHIOU , Tsung-Ding WANG
CPC分类号: H01L23/3114 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L24/16 , H01L24/32 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/68368 , H01L2221/68381 , H01L2224/16145 , H01L2224/32145 , H01L2224/80006 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2224/81005 , H01L2224/81801 , H01L2224/83005 , H01L2224/8385 , H01L2224/94 , H01L2224/95001 , H01L2225/06541 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/1421 , H01L2924/1431 , H01L2924/1434 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/3512 , H01L2924/00 , H01L2224/83
摘要: A method for thin wafer handling and processing is provided. In one embodiment, the method comprises providing a wafer having a plurality of semiconductor chips, the wafer having a first side and a second side. A plurality of dies are attached to the first side of the wafer, at least one of the dies are bonded to at least one of the plurality of semiconductor chips. A wafer carrier is provided, wherein the wafer carrier is attached to the second side of the wafer. The first side of the wafer and the plurality of dies are encapsulated with a planar support layer. A first adhesion tape is attached to the planar support layer. The wafer carrier is then removed from the wafer and the wafer is diced into individual semiconductor packages.
摘要翻译: 提供了一种用于薄晶片处理和处理的方法。 在一个实施例中,该方法包括提供具有多个半导体芯片的晶片,该晶片具有第一侧和第二侧。 多个管芯附接到晶片的第一侧,至少一个管芯被结合到多个半导体芯片中的至少一个。 提供晶片载体,其中晶片载体附接到晶片的第二侧。 晶片的第一侧和多个管芯被平坦的支撑层封装。 第一粘合带附接到平面支撑层。 然后将晶片载体从晶片上移除,并将晶片切成单独的半导体封装。
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公开(公告)号:US20100244247A1
公开(公告)日:2010-09-30
申请号:US12722949
申请日:2010-03-12
申请人: Hung-Pin CHANG , Wen-Chih CHIOU , Chen-Hua YU
发明人: Hung-Pin CHANG , Wen-Chih CHIOU , Chen-Hua YU
IPC分类号: H01L23/48 , H01L21/768
CPC分类号: H01L21/76898 , H01L2924/0002 , Y10S438/978 , H01L2924/00
摘要: A via etching process forms a through-substrate via having a round corner and a tapered sidewall profile. A method includes providing a semiconductor substrate; forming a hard mask layer and a patterned photoresist layer on the semiconductor substrate; forming an opening in the hard mask and exposing a portion of the semiconductor substrate; forming a via passing through at least a part of the of semiconductor substrate using the patterned photoresist layer and hard mask layer as a masking element; performing a trimming process to round the top corner of the via; and removing the photoresist layer.
摘要翻译: 通孔蚀刻工艺通过具有圆角和锥形侧壁轮廓形成通孔基板。 一种方法包括提供半导体衬底; 在所述半导体衬底上形成硬掩模层和图案化的光致抗蚀剂层; 在所述硬掩模中形成开口并暴露所述半导体衬底的一部分; 使用图案化的光致抗蚀剂层和硬掩模层作为掩模元件形成穿过半导体衬底的至少一部分的通孔; 执行修整过程以绕过通孔的顶角; 并除去光致抗蚀剂层。
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公开(公告)号:US20100164109A1
公开(公告)日:2010-07-01
申请号:US12345239
申请日:2008-12-29
申请人: Wen-Chih Chiou , Weng-Jin Wu
发明人: Wen-Chih Chiou , Weng-Jin Wu
IPC分类号: H01L23/538
CPC分类号: H01L24/05 , H01L21/6835 , H01L23/481 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2221/6834 , H01L2224/0231 , H01L2224/0401 , H01L2224/05568 , H01L2224/0557 , H01L2224/05599 , H01L2224/13025 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/13644 , H01L2224/81001 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2224/13099 , H01L2224/05552
摘要: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate. The TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. A silicide layer is over and contacting the RDL.
摘要翻译: 集成电路结构包括具有正面和背面的半导体衬底。 穿透硅通孔(TSV)穿透半导体衬底。 TSV具有延伸到半导体衬底背面的后端。 再分配线(RDL)位于半导体衬底的背面,并连接到TSV的后端。 硅化物层已经结束并与RDL接触。
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公开(公告)号:US20100144118A1
公开(公告)日:2010-06-10
申请号:US12330209
申请日:2008-12-08
申请人: Ku-Feng Yang , Weng-Jin Wu , Wen-Chih Chiou , Chen-Hua Yu
发明人: Ku-Feng Yang , Weng-Jin Wu , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号: H01L21/46 , H01L21/465
CPC分类号: H01L21/486 , H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/13009 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14181 , H01L2224/16146 , H01L2224/32145 , H01L2224/73203 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/01019 , H01L2224/11
摘要: A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer.
摘要翻译: 公开了一种用于堆叠半导体管芯的系统和方法。 优选实施例包括形成通过晶片的穿硅通孔,保护晶片的边缘边缘,然后去除未受保护的部分,使得边缘边缘的厚度大于薄的晶片。 该厚度有助于脆弱的晶片在进一步的运输和工艺步骤中保持生存。 然后优选在从晶片分离单个模具期间移除边缘。
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公开(公告)号:US20100140767A1
公开(公告)日:2010-06-10
申请号:US12329322
申请日:2008-12-05
申请人: Weng-Jin Wu , Hung-Jung Tu , Ku-Feng Yang , Jung-Chih Hu , Wen-Chih Chiou
发明人: Weng-Jin Wu , Hung-Jung Tu , Ku-Feng Yang , Jung-Chih Hu , Wen-Chih Chiou
CPC分类号: H01L23/3157 , H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2225/06513 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要: A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film.
摘要翻译: 一种形成集成电路的方法包括将包括开口的图案化膜层压到晶片上,其中晶片中的底模裸露通过开口。 将顶模放入开口。 顶部模具装配到开口中,在图案化膜和顶模之间基本上没有间隙。 然后将顶模结合到底模上,随后固化图案化膜。
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