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53 条记录 (耗时 0.045 秒)

    SYSTEM AND METHOD FOR AUTHENTICATING PHARMACEUTICALS USING INTERNALLY LOCATED HYDROSCOPIC GELS WITH INDICIA
    33.
    发明申请
    SYSTEM AND METHOD FOR AUTHENTICATING PHARMACEUTICALS USING INTERNALLY LOCATED HYDROSCOPIC GELS WITH INDICIA 有权
    用INDIIA内部定位的胶体凝胶来确认药物的系统和方法

    公开(公告)号：US20090269286A1

    公开(公告)日：2009-10-29

    申请号：US12111503

    申请日：2008-04-29

    申请人： George F. Walker

    发明人： George F. Walker

    IPC分类号： A61K9/44

    CPC分类号： A61K9/2072 ,  A61J3/007 ,  A61J2200/20 ,  A61J2205/10 ,  A61J2205/20 ,  A61J2205/40 ,  A61J2205/50

    摘要： The invention is an article of manufacture, comprising an identifying marker disposed in a pharmaceutical product. The pharmaceutical product may be selected from the group consisting of a pharmaceutical liquid, a pill, a tablet, a caplet, and a capsule. The identifying marker may be a hydroscopic medium having an indicia imprinted thereon or within, where the marker expands volumetrically when contacted with a liquid.

    摘要翻译： 本发明是一种制品，其包括设置在药品中的识别标记。 药物产品可以选自药物液体，丸剂，片剂，囊片和胶囊。 识别标记物可以是具有印记在其上或内部的标记的吸湿介质，其中当与液体接触时，标记物在体积上膨胀。

    High density space transformer and method of fabricating same
    34.
    发明授权
    High density space transformer and method of fabricating same 失效
    高密度空间变压器及其制造方法

    公开(公告)号：US07252514B2

    公开(公告)日：2007-08-07

    申请号：US10931428

    申请日：2004-09-02

    申请人： Samuel R. McKnight ,  George F. Walker

    发明人： Samuel R. McKnight ,  George F. Walker

    IPC分类号： H01R12/00 ,  H05K1/00

    CPC分类号： H01R9/0515 ,  G01R1/06772 ,  G01R1/07378

    摘要： A method for forming a space transformer (and a space transformer formed by the method) having a first plate and a second plate, the plates being separated by a frame, and electrical connectors for providing electrical connections between electrical contacts which are relatively closely spaced on the first plate and relatively more widely spaced on the second plate. The method comprises attaching first ends of wires to first electrically conductive regions on the first plate; forming insulating layers over the wires; forming electrically conductive coverings over the insulating layers; and connecting second ends of the wires to second electrically conductive regions on the second plate.

    摘要翻译： 一种用于形成具有第一板和第二板的空间变压器（和由该方法形成的空间变压器）的方法，所述板由框架分隔开，并且电连接器用于在电触点之间提供电连接，所述电触点相对紧密地间隔开 第一板并且在第二板上相对更宽的间隔。 该方法包括将导线的第一端附接到第一板上的第一导电区域; 在导线上形成绝缘层; 在绝缘层上形成导电覆盖物; 并且将所述导线的第二端连接到所述第二板上的第二导电区域。

    Semiconductor wafer test and burn-in
    37.
    发明授权
    Semiconductor wafer test and burn-in 失效
    半导体晶圆测试和老化

    公开(公告)号：US5600257A

    公开(公告)日：1997-02-04

    申请号：US513057

    申请日：1995-08-09

    申请人： James M. Leas ,  Robert W. Koss ,  George F. Walker ,  Charles H. Perry ,  Jody J. Van Horn

    发明人： James M. Leas ,  Robert W. Koss ,  George F. Walker ,  Charles H. Perry ,  Jody J. Van Horn

    IPC分类号： G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R1/02

    CPC分类号： G01R1/07385 ,  G01R1/07314 ,  G01R31/2889 ,  G01R31/2863 ,  G01R31/2879 ,  G01R31/2886

    摘要： An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

    摘要翻译： 用于在产品晶片上的所有集成电路芯片中同时测试或燃烧的装置和方法。 该装置包括具有测试芯片的玻璃陶瓷载体和用于连接到产品晶片上的大量芯片的焊盘的装置。 测试芯片上的电压调节器提供电源和产品芯片上的电源接口之间的接口，每个产品芯片至少有一个电压调节器。 电压调节器向产品芯片提供指定的Vdd电压，由此Vdd电压基本上与产品芯片所消耗的电流无关。 电压调节器或其他电子装置将电流限制在任何产品芯片上。 电压调节器电路可以是门控和可变的，并且其可以具有延伸到产品芯片的传感器线路。 测试芯片还可以提供测试功能，例如测试模式和用于存储测试结果的寄存器。

    Spring array connector
    38.
    发明授权
    Spring array connector 失效
    弹簧阵列连接器

    公开(公告)号：US5299939A

    公开(公告)日：1994-04-05

    申请号：US847970

    申请日：1992-03-05

    申请人： George F. Walker ,  Arthur Zingher

    发明人： George F. Walker ,  Arthur Zingher

    IPC分类号： H01R13/24 ,  H01R12/71 ,  H01R13/33 ,  H01R24/00 ,  H01R9/09

    CPC分类号： H01R13/33 ,  H01R12/57 ,  H01R12/714 ,  H01R13/24

    摘要： A spring array connector includes a unitary resilient layer of multiple springs having a layer of multiple electrically conducting lines, electrical contacts and electrical terminals. Each spring of the array is independently bendable and each of the conducting lines is electrically isolated from the other conducting lines. All of the springs in the spring array are fabricated simultaneously. Spring embodiments include sine, helix, cantilever and buckling beam shapes in sheet and wire forms.

    摘要翻译： 弹簧阵列连接器包括具有多个导电线，电触头和电端子层的多个弹簧的单一弹性层。 阵列的每个弹簧都是可独立弯曲的，并且每条导线与其它导线电隔离。 弹簧阵列中的所有弹簧都是同时制造的。 弹簧实施例包括片材和线材形式的正弦，螺旋，悬臂和屈曲梁形状。

    Semiconductor device having metallic interconnects formed by grit blasting
    40.
    发明授权
    Semiconductor device having metallic interconnects formed by grit blasting 失效
    具有通过喷砂形成的金属互连的半导体装置

    公开(公告)号：US5170245A

    公开(公告)日：1992-12-08

    申请号：US653978

    申请日：1991-02-11

    申请人： Jungihl Kim ,  Joseph C. Logue ,  John J. Ritsko ,  Robert R. Shaw ,  George F. Walker

    发明人： Jungihl Kim ,  Joseph C. Logue ,  John J. Ritsko ,  Robert R. Shaw ,  George F. Walker

    IPC分类号： B24C1/04 ,  B24C3/32 ,  H01L21/48 ,  H05K1/03 ,  H05K3/00

    CPC分类号： H01L21/4807 ,  B24C1/04 ,  B24C3/322 ,  H01L21/486 ,  H05K3/0044 ,  H05K1/0306 ,  H05K2203/025 ,  H05K3/4629

    摘要： This invention relates to a ceramic module and to methods for forming protruding, upstanding electrically conducting pins by the selective abrasion of a surface 18 of a multilayered ceramic module 10. An abrasive blasting device 40 is disposed adjacent to the surface 18 for directing a stream of abrasive particles 42 against the surface. The particles 42 strike both metallic conductors 20 and 22 and also the ceramic material of the layer 14. Inasmuch as the ceramic material is relatively hard and brittle as compared to the ductile metallic conductors the abrasive particles 42 abrade away the ceramic layer 14 at a faster rate than the ductile metallic material of the conductors 20 and 22. The abrasive particles 42 may be comprised of any suitable abrasive, such as Al.sub.2 O.sub.3, SiC or WC. The module may be rotated beneath a nozzle of the grit blasting device, the nozzle being linearly translated above the surface being abraded.

    摘要翻译： 本发明涉及一种陶瓷模块以及通过多层陶瓷模块10的表面18的选择性磨损来形成突出的，直立的导电销的方法。喷砂装置40邻近表面18设置，用于引导 研磨颗粒42抵靠表面。 颗粒42撞击金属导体20和22以及层14的陶瓷材料。由于与延性金属导体相比，陶瓷材料相对硬且脆，研磨颗粒42以更快的速度磨掉陶瓷层14 导体20和22的韧性金属材料的比率。磨料颗粒42可以由任何合适的研磨剂，例如Al 2 O 3，SiC或WC组成。 模块可以在喷砂装置的喷嘴下方旋转，喷嘴在被磨损的表面上线性平移。