公开(公告)号：US20170103961A1

公开(公告)日：2017-04-13

申请号：US15388166

申请日：2016-12-22

Applicant: Micron Technology, Inc.

Inventor： Choon Kuan Lee ,  Chin Hui Chong ,  David J. Corisis

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/29 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/29005 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

公开(公告)号：US09362208B2

公开(公告)日：2016-06-07

申请号：US14821550

申请日：2015-08-07

Applicant: Micron Technology, Inc.

Inventor： Matt E. Schwab ,  J. Michael Brooks ,  David J. Corisis

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/492 ,  H01L23/16 ,  H01L23/31 ,  H01L25/065 ,  H01L23/36 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L23/16 ,  H01L23/36 ,  H01L23/4924 ,  H01L24/06 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.

Abstract translation: 公开了具有基本刚性支撑构件的封装半导体部件。 封装可以包括半导体管芯和靠近半导体管芯的支撑构件。 支撑构件至少基本上是刚性的。 包装件还可以包括在支撑构件和半导体管芯之间的粘合剂，并且将支撑构件粘合地附接到半导体管芯。 封装还可以包括承载半导体管芯的衬底和附接到半导体管芯的支撑构件。

公开(公告)号：US09362141B2

公开(公告)日：2016-06-07

申请号：US13898004

申请日：2013-05-20

Applicant: Micron Technology, Inc.

Inventor： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC: H01L21/58 ,  H01L21/56 ,  H01L25/065 ,  H01L25/11 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L21/66

CPC classification number: H01L23/053 ,  H01L21/56 ,  H01L21/561 ,  H01L22/10 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49805 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06503 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

公开(公告)号：US09142427B2

公开(公告)日：2015-09-22

申请号：US14180567

申请日：2014-02-14

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  David J. Corisis ,  Choon Kuan Lee

IPC: H01L29/00 ,  H01L21/4763 ,  H01L21/48 ,  H01L23/50 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L21/4857 ,  H01L23/50 ,  H01L24/82 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening.

Abstract translation: 公开了一种包括插入器的至少一个电容器，至少部分地形成在插入器中形成的开口内的至少一个电容器和可操作地耦合到插入器的集成电路。 公开了一种方法，其包括获得具有至少部分地在插入器中的开口内形成的至少一个电容器并且将集成电路可操作地耦合到插入器的插入器。 还公开了一种方法，其包括获得包括电介质材料的插入件，在插入器中形成开口并形成至少部分位于开口内的电容器。

公开(公告)号：US20150156908A1

公开(公告)日：2015-06-04

申请号：US14617523

申请日：2015-02-09

Applicant: Micron Technology, Inc.

Inventor： Kevin Gibbons ,  Tracy V. Reynolds ,  David J. Corisis

IPC: H05K7/02 ,  H05K1/11

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19104 ,  H05K1/111 ,  H05K1/182 ,  H05K1/183 ,  H05K3/3436 ,  H05K7/02 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10727 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.

Abstract translation: 公开了具有小厚度和相关制造方法的计算机模块。 在一个实施例中，计算机模块可以包括具有模块材料和至少部分延伸到模块材料中的孔的模块衬底。 计算机模块还可以包括由模块衬底承载的微电子封装。 微电子封装包括由封装衬底承载的半导体管芯。 半导体管芯的至少一部分经由孔延伸到衬底材料中。

公开(公告)号：US08975745B2

公开(公告)日：2015-03-10

申请号：US13893638

申请日：2013-05-14

Applicant: Micron Technology, Inc.

Inventor： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC: H01L23/498 ,  H01L23/24 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/24 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes positioning a microelectronic device in a cavity of a support member, with the cavity having a closed end with a conductive layer, and an opening through which the cavity is assessable. The microelectronic device can have bond sites, a first surface, and a second surface facing opposite from the first surface. The microelectronic device can be positioned in the cavity so that the second surface faces toward and is carried by the conductive layer. The method can further include electrically coupling the bond sites of the microelectronic device to the conductive layer. In particular embodiments, the microelectronic device can be encapsulated in the cavity without the need for a releasable tape layer to temporarily support the microelectronic device.

Abstract translation: 封装在支撑构件空腔中的微电子器件以及相关方法被公开。 根据一个实施例的方法包括将微电子器件定位在支撑构件的空腔中，其中空腔具有带有导电层的封闭端以及空腔可以评估的开口。 微电子器件可以具有接合位置，第一表面和与第一表面相对的第二表面。 微电子器件可以定位在空腔中，使得第二表面面向导电层并由导电层承载。 该方法还可以包括将微电子器件的键合位置电耦合到导电层。 在具体实施例中，微电子器件可以被封装在空腔中，而不需要可释放的带层来临时支撑微电子器件。

公开(公告)号：US20150021769A1

公开(公告)日：2015-01-22

申请号：US14506423

申请日：2014-10-03

Applicant: Micron Technology, Inc.

Inventor： Matt E. Schwab ,  David J. Corisis ,  J. Michael Brooks

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/09 ,  H01L24/17 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/11011 ,  H01L2224/13111 ,  H01L2224/1405 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

Abstract translation: 公开了用于制造封装的微电子器件的封装的微电子器件和方法。 在一个实施例中，用于形成微电子器件的方法包括通过在微电子管芯的背面和支撑构件的至少一个上形成附着特征来将微电子管芯附接到支撑构件。 附件特征包括一定量的焊料。 该方法还包括使附接特征与另一个微电子管芯和支撑构件接触，以及回流焊料材料以经由附接特征连接到管芯的背面和支撑构件。 在几个实施例中，附接特征不与管芯的内部有源结构电连接。

公开(公告)号：US20140342476A1

公开(公告)日：2014-11-20

申请号：US14450998

申请日：2014-08-04

Applicant: Micron Technology, Inc.

Inventor： Lee Choon Kuan ,  David J. Corisis ,  Chin Hui Chong

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/00

CPC classification number: H01L24/92 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/49531 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92127 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. Terminal pads of the interposer substrate may be electrically connected to either or both of a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. Additional components, active, passive or both, may be connected to pads of the two-dimensional array to provide a system-in-a-package. Lead fingers of a lead frame may be superimposed on the opposing side of the interposer substrate, bonded directly to the land grid array land and wire bonded to pads as desired for repair or to ease routing problems on the interposer. The land grid array package may be mounted to a carrier substrate, and the lands wire bonded to conductive pads on the carrier substrate. Methods of fabrication are also disclosed.

Abstract translation: 半导体器件封装包括焊盘栅格阵列封装。 至少一个半导体管芯安装到插入器衬底上，其中半导体管芯的接合焊盘连接到与至少一个半导体管芯在内插器衬底的同一侧上的端子焊盘。 插入器基板的端子焊盘可以电连接到焊盘的外围阵列图案中的一个或两个以及中心的二维阵列阵列图案，两个阵列图案位于至少从中间层基板的相对侧起至少 一个半导体芯片。 可以将主动，被动或两者的附加组件连接到二维阵列的焊盘以提供系统级封装。 引线框架的引脚可以叠置在插入器基板的相对侧上，直接接合到焊盘栅格阵列焊盘，并且焊接到焊盘上，以便修理或者简化插入器上的布线问题。 焊盘阵列封装可以安装到载体衬底上，焊盘引线键合到载体衬底上的导电焊盘上。 还公开了制造方法。

公开(公告)号：US20130292810A1

公开(公告)日：2013-11-07

申请号：US13933294

申请日：2013-07-02

Applicant: Micron Technology, Inc.

Inventor： Choon Kuan Lee ,  David J. Corisis ,  Chong Chin Hui

IPC: H05K1/11 ,  H01L23/495

CPC classification number: H05K1/113 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/48 ,  H01L24/82 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/30107 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.

Abstract translation: 芯片级片上基板或再分配元件的制造方法包括在基板的相对侧上形成导电平面。 导电平面中的第一个包括两组键合指状物，从第一组键合指状物延伸的导电迹线和两组再分布的键合焊盘，包括导电迹线引导到的第一组。 第二导电平面包括从与第二组键合指状物相对的位置朝向与第二组再分布接合焊盘的位置相反的位置延伸的导电迹线。 导电通孔通过第二组接合指形成到第二导电平面的导电迹线。 此外，还形成导电通孔，以将第二导电平面的导电通孔与第一导电平面中相应的再分布接合焊盘电连接。

公开(公告)号：US20130252354A1

公开(公告)日：2013-09-26

申请号：US13898004

申请日：2013-05-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC: H01L21/56

CPC classification number: H01L23/053 ,  H01L21/56 ,  H01L21/561 ,  H01L22/10 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49805 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06503 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

Abstract translation: 本文公开了堆叠的微电子器件和用于制造这种器件的方法。 在一个实施例中，堆叠的微电子器件组件可以包括包括第一插入器衬底的第一已知的良好封装的微电子器件。 第一管芯和第一穿通管互连件电耦合到第一插入器衬底。 第一壳体至少部分地封装第一装置，使得每个第一互连件的一部分在第一壳体的顶部可接近。 第二已知的良好封装的微电子器件以堆叠配置耦合到第一器件。 第二器件可以包括具有多个第二插入器焊盘的第二插入器衬底和与第二插入器衬底电耦合的第二管芯。 第一互连的暴露部分电耦合到对应的第二插入器焊盘。