公开(公告)号：US20150249065A1

公开(公告)日：2015-09-03

申请号：US14710393

申请日：2015-05-12

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81024 ,  H01L2224/81201 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.

Abstract translation: 半导体器件具有第一衬底，其具有部分地穿过第一衬底形成的多个第一导电通孔。 第一半导体管芯安装在第一衬底上并电连接到第一导电通孔。 在第一基板上形成多个凸块。 第二衬底具有部分地穿过第二衬底形成的多个第二导电通孔。 可渗透的密封剂沉积在第二基底上。 将第二衬底安装在第一衬底上以将第一半导体管芯和互连结构嵌入可渗透的密封剂中。 密封剂可以注射在第一和第二基底之间。 去除第一衬底的一部分以露出第一导电通孔。 去除第二衬底的一部分以暴露第二导电通孔。 第二半导体管芯安装在第二衬底上。

公开(公告)号：US09123663B2

公开(公告)日：2015-09-01

申请号：US12136682

申请日：2008-06-10

Applicant: OhHan Kim ,  SeungWon Kim ,  JoungUn Park

Inventor： OhHan Kim ,  SeungWon Kim ,  JoungUn Park

IPC: H01L21/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/29 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A shielded semiconductor device is made by mounting semiconductor die to a first substrate. An encapsulant is formed over the semiconductor die and first substrate. A dicing channel is formed through the encapsulant between the semiconductor die. A hole is drilled in the first substrate along the dicing channel on each side of the semiconductor die. A shielding layer is formed over the encapsulant and semiconductor die. The hole is lined with the shielding layer. The first substrate is singulated to separate the semiconductor die. The first substrate is mounted to a second substrate. A metal pillar is formed in the opening to electrically connect the shielding layer to a ground plane in the second substrate. The metal pillar includes a hook for a mechanically secure connection to the shielding layer. An interconnect structure is formed on the first substrate to electrically connect the semiconductor die to the second substrate.

Abstract translation: 通过将半导体管芯安装到第一基板上来制造屏蔽半导体器件。 在半导体管芯和第一基板上形成密封剂。 通过半导体管芯之间的密封剂形成切割通道。 沿着半导体管芯的每一侧上的切割通道在第一基板中钻出一个孔。 在密封剂和半导体管芯上方形成屏蔽层。 孔内衬有屏蔽层。 单个第一衬底以分离半导体管芯。 第一基板安装到第二基板。 金属柱形成在开口中，以将屏蔽层电连接到第二基板中的接地平面。 金属柱包括用于与屏蔽层机械固定连接的钩。 在第一基板上形成互连结构，以将半导体管芯电连接到第二基板。

公开(公告)号：US09082638B2

公开(公告)日：2015-07-14

申请号：US13572517

申请日：2012-08-10

Applicant: YongTaek Lee ,  Gwang Kim ,  ByungHoon Ahn

Inventor： YongTaek Lee ,  Gwang Kim ,  ByungHoon Ahn

IPC: H01L29/00 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L27/08 ,  H01L23/5223 ,  H01L23/5225 ,  H01L27/1203 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.

Abstract translation: 通过在衬底上形成氧化物层并在氧化物层上形成第一导电层来制造半导体器件。 第一导电层连接到地面。 在第一导电层上形成第二导电层作为多个段。 在第二导电层上形成第三导电层作为多个段。 如果导电层是电隔离的，则通过这些层形成导电通孔。 第三导电层的第一段作为第一无源电路元件工作。 第二段作为第二无源电路元件工作。 第三段连接到地面并作为设置在第一和第二段之间的屏蔽来操作。 屏蔽件的高度至少等于无源电路元件的高度，以阻止无源电路元件之间的串扰。

公开(公告)号：US09076803B2

公开(公告)日：2015-07-07

申请号：US14063274

申请日：2013-10-25

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/81805

Abstract: A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

Abstract translation: 半导体器件具有第一互连结构。 第一半导体管芯具有朝向并安装到第一互连结构的第一表面的有源表面。 第一密封剂沉积在第一互连结构和第一半导体管芯上。 第二半导体管芯具有朝向并安装到与第一表面相对的第一互连结构的第二表面的有源表面。 多个第一导电柱形成在第一互连结构的第二表面上并且围绕第二半导体管芯。 第二密封剂沉积在第二半导体管芯上并围绕多个第一导电柱。 包括导电层和凸块的第二互连结构形成在第二密封剂上并且电连接到多个第一导电柱和第一和第二半导体管芯。

公开(公告)号：US09076802B1

公开(公告)日：2015-07-07

申请号：US14037320

申请日：2013-09-25

Applicant: WonJun Ko ,  GwangTae Kim ,  KeoChang Lee

Inventor： WonJun Ko ,  GwangTae Kim ,  KeoChang Lee

IPC: H01L23/28 ,  H01L21/00 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/565 ,  H01L23/3121 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00

Abstract: Simultaneous semiconductor packages can be produced using a dual-sided film-assist molding process. The process involves using a film or membrane having opposing surfaces for receiving un-encapsulated semiconductor packages on both surfaces. A slot can be formed in the film or membrane to facilitate introduction and passage of the encapsulation therethrough such that upon removal of the film or membrane, increased throughput and productivity of the completed semiconductor packages can be carried out to achieve considerable cost savings.

Abstract translation: 可以使用双面胶片辅助成型工艺制造同时半导体封装。 该方法涉及使用具有相对表面的膜或膜来在两个表面上接收未封装的半导体封装。 可以在膜或膜中形成狭槽以便于通过其中的封装的引入和通过，使得在去除膜或膜时，可以进行完成的半导体封装的增加的生产率和生产率以实现显着的成本节约。

公开(公告)号：US20150171024A1

公开(公告)日：2015-06-18

申请号：US14109313

申请日：2013-12-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Pandi C. Marimuthu

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A semiconductor device has a substrate including a base substrate material and a plurality of conductive vias formed partially though the substrate. A plurality of semiconductor die including a base semiconductor material is disposed over the substrate. A ratio of an encapsulant to a quantity of the semiconductor die is determined for providing structural support for the semiconductor die. An encapsulant is deposited over the semiconductor die and substrate. An amount of the encapsulant is selected based on the determined ratio or based on a total amount of the base substrate material and base semiconductor material. Channels are formed in the encapsulant by removing a portion of the encapsulant in a peripheral region of the semiconductor die. Alternatively, a side surface of the semiconductor die is partially exposed with respect to the encapsulant. A portion of the base substrate material is removed to expose the conductive vias.

Abstract translation: 半导体器件具有包括基底材料和部分地通过衬底形成的多个导电通孔的衬底。 包括基底半导体材料的多个半导体管芯设置在基板上。 确定密封剂与半导体管芯的量的比率以提供半导体管芯的结构支撑。 密封剂沉积在半导体管芯和衬底上。 基于确定的比例或基于基底材料和基底半导体材料的总量来选择一定量的密封剂。 通过在半导体管芯的周边区域中去除一部分密封剂而在密封剂中形成通道。 或者，半导体管芯的侧表面相对于密封剂部分地露出。 去除基底衬底材料的一部分以露出导电通孔。

公开(公告)号：US09059157B2

公开(公告)日：2015-06-16

申请号：US13842582

申请日：2013-03-15

Applicant: Yaojian Lin ,  Il Kwon Shim ,  JunMo Koo ,  Jose Alvin Caparas

Inventor： Yaojian Lin ,  Il Kwon Shim ,  JunMo Koo ,  Jose Alvin Caparas

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L23/16

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/16 ,  H01L23/49816 ,  H01L24/19 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a top insulation layer and a top conductive layer; an inter-react layer on the substrate; an integrated circuit die on the substrate; a package body on the inter-react layer and the integrated circuit die; and a top solder bump on the top conductive layer, the top solder bump in a 3D via formed through the package body, the inter-react layer, and the top insulation layer for exposing the top conductive layer in the 3D via.

Abstract translation: 集成电路封装系统及其制造方法包括：具有顶部绝缘层和顶部导电层的衬底; 基板上的反应间层; 集成电路裸片在基板上; 反应层间和集成电路管芯上的封装体; 以及顶部导电层上的顶部焊料凸块，通过封装主体，反应间层和顶部绝缘层形成的3D通孔中的顶部焊料凸块，用于暴露3D通孔中的顶部导电层。

公开(公告)号：US09054100B2

公开(公告)日：2015-06-09

申请号：US13287006

申请日：2011-11-01

Applicant: JaeHyun Lee ,  KiYoun Jang

Inventor： JaeHyun Lee ,  KiYoun Jang

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L21/563 ,  H01L24/27 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/00

Abstract: A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over a substrate. A patterning layer is formed over the substrate. A first portion of the patterning layer is removed to form an opening to expose the substrate and conductive layer. A second portion of the patterning layer is removed to form a sloped surface in the patterning layer extending from a surface of the patterning layer down to the substrate. The sloped surface in the patterning layer can be linear, concave, or convex. The die is mounted to the substrate with the composite bump structures electrically connected to the conductive layer. An underfill material is deposited over the surface of the patterning layer. The sloped surface in the patterning layer aids with the flow of underfill material to cover an area between the die and substrate.

Abstract translation: 半导体器件具有在半导体管芯的表面上的复合凸块结构的半导体管芯。 在衬底上形成导电层。 在衬底上形成图形层。 去除图形层的第一部分以形成开口以暴露衬底和导电层。 图案化层的第二部分被去除以在图案形成层中形成从图案形成层的表面向下延伸到衬底的倾斜表面。 图案化层中的倾斜表面可以是线形，凹形或凸形。 模具安装到基板上，复合凸块结构电连接到导电层。 在图案化层的表面上沉积底部填充材料。 图案化层中的倾斜表面有助于底部填充材料的流动以覆盖管芯和基底之间的区域。

公开(公告)号：US20150155248A1

公开(公告)日：2015-06-04

申请号：US14616942

申请日：2015-02-09

Applicant: STATS CHIPPAC, LTD.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2223/5448 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 μm larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.

Abstract translation: 半导体器件包括具有导电层的半导体管芯。 在半导体管芯和导电层上形成第一绝缘层。 密封剂设置在半导体管芯上。 在第一绝缘层上形成顺应性岛。 互连结构形成在柔性岛上。 凸块金属化（UBM）形成在柔性岛上。 柔性岛包括比UBM的直径大大于5μm的直径。 在导电层上的柔性岛中形成开口。 在第一绝缘层和顺应性岛上形成第二绝缘层。 在半导体管芯和密封剂之间的界面上形成第三绝缘层。 在密封剂上的第三绝缘层中形成开口以消除应力。

公开(公告)号：US09048209B2

公开(公告)日：2015-06-02

申请号：US13190339

申请日：2011-07-25

Applicant: JiHoon Oh ,  SinJae Lee ,  JinGwan Kim

Inventor： JiHoon Oh ,  SinJae Lee ,  JinGwan Kim

IPC: H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/14 ,  H01L23/06 ,  H01L23/10 ,  H01L23/15 ,  H01L23/36 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/52 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer.

Abstract translation: 通过在载体上形成散热器来制造半导体器件。 半导体管芯安装在散热器上方，第一表面朝向散热器。 第一绝缘层形成在半导体管芯和散热器上。 在第一绝缘层中形成通孔。 第一导电层形成在第一绝缘层之上，并通过通孔和半导体管芯上的接触焊盘连接到散热器。 散热器从半导体管芯的第一表面延伸到通孔。 在第一导电层上形成第二绝缘层。 第二导电层电连接到第一导电层。 载体被移除。 散热器从半导体管芯散热，并提供屏蔽器件间干扰。 散热器通过第一导电层接地。