公开(公告)号：US20110221055A1

公开(公告)日：2011-09-15

申请号：US12724367

申请日：2010-03-15

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/48 ,  H01L21/78 ,  H01L21/60 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/76879 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2223/5448 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

Abstract translation: 半导体晶片具有多个第一半导体管芯。 在模具的有效表面上形成第一导电层。 在有源表面和第一导电层上形成第一绝缘层。 在第一绝缘层和第一导电层上形成再钝化层。 通过再钝化层形成通孔至第一导电层。 单个半导体晶片以分离半导体管芯。 半导体管芯安装在临时载体上。 密封剂沉积在半导体管芯和载体上。 载体被移除。 在再钝化层和密封剂上形成第二绝缘层。 在再钝化层和第一导电层上形成第二导电层。 在第二导电层和第二绝缘层上形成第三绝缘层。 在第二导电层上形成互连结构。

公开(公告)号：US20110204505A1

公开(公告)日：2011-08-25

申请号：US12710995

申请日：2010-02-23

Applicant: Reza A. Pagaila ,  Yaojian Lin ,  Seung Uk Yoon

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Seung Uk Yoon

IPC: H01L25/065 ,  H01L21/70 ,  H01L23/52

CPC classification number: H01L23/5384 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/48247 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV.

Abstract translation: 半导体器件具有安装在载体上的半导体管芯。 密封剂沉积在半导体管芯和载体上。 在半导体管芯和密封剂上形成绝缘层。 在安装到载体上时，通过绝缘层和半导体管芯形成多个第一通孔。 在将半导体管芯安装到载体上的同时，通过绝缘层和密封剂沿与第一通孔相同的方向形成多个第二通孔。 在第一通孔中沉积导电材料以形成导电TSV，并在第二通孔中形成导电TMV。 第一互连结构形成在绝缘层上并电连接到TSV和TMV。 载体被移除。 第二互连结构形成在半导体管芯和密封剂上并电连接到TSV和TMV。

公开(公告)号：US20110127668A1

公开(公告)日：2011-06-02

申请号：US12628631

申请日：2009-12-01

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen

IPC: H01L23/498 ,  H01L21/60 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/29 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05155 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1411 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

Abstract translation: 半导体晶片具有在其有效表面上形成的第一导电层。 第一绝缘层形成在衬底和第一导电层上。 在第一导电层和第一绝缘层上形成第二导电层。 在第二导电层上方的凸块形成区域周围形成UBM层。 UBM层可以是两个堆叠的金属层或三个堆叠的金属层。 第二导电层暴露在凸块形成区域中。 在UBM层和第二导电层上形成第二绝缘层。 第二绝缘层的一部分在凸块形成区域和UBM层的一部分上被去除。 在凸块形成区域中的第二导电层上形成凸块。 凸块接触UBM层以密封凸点和第二导电层之间的接触界面。

公开(公告)号：US20110115050A1

公开(公告)日：2011-05-19

申请号：US12621738

申请日：2009-11-19

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/10 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L27/016 ,  H01L28/24 ,  H01L28/60 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73207 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.

Abstract translation: 通过在追逐模具的第一和第二板之间沉积密封材料以形成模制基底来制造半导体器件。 在模制的基底上形成第一导电层。 在第一导电层上形成电阻层。 在电阻层上形成第一绝缘层。 在第一绝缘层，电阻层，第一导电层和模制衬底之上形成第二绝缘层。 在第一绝缘层，电阻层和第一导电层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 在第二导电层上形成凸块。 第一导电层，电阻层，第一绝缘层和第二导电层构成MIM电容器。 第二导电层被卷绕以表现出感应特性。

公开(公告)号：US07935570B2

公开(公告)日：2011-05-03

申请号：US12331698

申请日：2008-12-10

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L21/00

CPC classification number: H01L23/3135 ,  H01L23/24 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/552 ,  H01L23/66 ,  H01L24/24 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a first insulation layer formed over a sacrificial substrate. A first conductive layer is formed over the first insulating layer. Conductive pillars are formed over the first conductive layer. A pre-fabricated IPD is disposed between the conductive pillars. An encapsulant is formed around the IPD and conductive pillars. A second insulation layer is formed over the encapsulant. The conductive pillars are electrically connected to the first and second conductive layers. The first and second conductive layers each include an inductor. Semiconductor devices are mounted over the first and second insulating layer and electrically connected to the first and second conductive layers, respectively. An interconnect structure is formed over the first and second insulating layers, respectively, and electrically connected to the first and second conductive layers. The sacrificial substrate is removed. The semiconductor devices can be stacked and electrically interconnected through the conductive pillars.

Abstract translation: 半导体器件具有形成在牺牲衬底上的第一绝缘层。 在第一绝缘层上形成第一导电层。 导电柱形成在第一导电层上。 预制IPD设置在导电柱之间。 在IPD和导电柱周围形成密封剂。 在密封剂上形成第二绝缘层。 导电柱电连接到第一和第二导电层。 第一和第二导电层各自包括电感器。 半导体器件安装在第一和第二绝缘层上，并分别电连接到第一和第二导电层。 互连结构分别形成在第一和第二绝缘层上，并且电连接到第一和第二导电层。 去除牺牲衬底。 半导体器件可以通过导电柱堆叠和电互连。

公开(公告)号：US20110049687A1

公开(公告)日：2011-03-03

申请号：US12942084

申请日：2010-11-09

Applicant: Heap Hoe Kuan ,  Rui Huang ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Heap Hoe Kuan ,  Rui Huang ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/49861 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/495 ,  H01L23/49506 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of manufacturing a semiconductor package system includes: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.

Abstract translation: 制造半导体封装系统的方法包括：形成具有无源器件的引线框架; 封装无源器件以形成密封介质; 将第一管芯附接到所述密封剂插入件; 形成具有第二管芯的基板插入件; 并且将所述密封剂插入物堆叠在所述基板插入件上。

公开(公告)号：US07843047B2

公开(公告)日：2010-11-30

申请号：US12276297

申请日：2008-11-21

Applicant: Heap Hoe Kuan ,  Rui Huang ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Heap Hoe Kuan ,  Rui Huang ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/495

CPC classification number: H01L23/49861 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/495 ,  H01L23/49506 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of manufacturing a semiconductor package system including: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.

Abstract translation: 一种制造半导体封装系统的方法，包括：形成具有无源器件的引线框架; 封装无源器件以形成密封介质; 将第一管芯附接到所述密封剂插入件; 形成具有第二管芯的基板插入件; 并且将所述密封剂插入物堆叠在所述基板插入件上。

公开(公告)号：US20100289126A1

公开(公告)日：2010-11-18

申请号：US12467908

申请日：2009-05-18

Applicant: Reza A. Pagaila ,  Yaojian Lin

Inventor： Reza A. Pagaila ,  Yaojian Lin

IPC: H01L23/552 ,  H01L21/50

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by mounting a semiconductor die over a carrier. A ferromagnetic inductor core is formed over the carrier. A prefabricated pillar frame is formed over the carrier, semiconductor die, and inductor core. An encapsulant is deposited over the semiconductor die and inductor core. A portion of the pillar frame is removed. A remaining portion of the pillar frame provides an interconnect pillar and inductor pillars around the inductor core. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors. In another embodiment, a shielding layer is formed over the semiconductor die. A capacitor or resistor is formed within the first or second interconnect structures.

Abstract translation: 半导体器件通过将半导体管芯安装在载体上而制成。 在载体上形成铁磁感应芯。 在载体，半导体管芯和电感器芯上形成预制柱架。 密封剂沉积在半导体管芯和电感器芯上。 取下柱框架的一部分。 柱框架的剩余部分在电感器芯周围提供互连柱和电感器柱。 在密封剂的第一表面上形成第一互连结构。 载体被移除。 在密封剂的第二表面上形成第二互连结构。 第一和第二互连结构电连接到电感器柱以形成一个或多个3D电感器。 在另一个实施例中，在半导体管芯上形成屏蔽层。 在第一或第二互连结构内形成电容器或电阻器。

公开(公告)号：US07767496B2

公开(公告)日：2010-08-03

申请号：US11957101

申请日：2007-12-14

Applicant: Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device is made by first forming a protective layer over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract translation: 半导体器件通过首先在半导体晶片的有效表面上形成保护层来制造。 具有预先施加的保护层的半导体管芯从半导体晶片移动并安装在载体上。 载体上的半导体管芯和接触焊盘被封装。 载体被移除。 在预先施加的保护层和接触垫上形成第一绝缘层。 在第一绝缘层和预先施加的保护层中形成通孔以暴露半导体管芯上的互连部位。 在第一绝缘层上形成互连结构，与半导体管芯和接触焊盘上的互连部位电接触。 互连结构具有形成在第一绝缘层上的再分布层，形成在再分配层上的第二绝缘层和形成在与再分布层电接触的第二电介质上的凸块下金属化层。

公开(公告)号：US20100059855A1

公开(公告)日：2010-03-11

申请号：US12207332

申请日：2008-09-09

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L29/00 ,  H01L21/00

CPC classification number: H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer.

Abstract translation: 通过提供用于支撑半导体器件的临时载体来制造半导体器件。 使用粘合剂将集成无源器件（IPD）安装到临时载体上。 IPD包括电容器和电阻器，并且具有多个穿硅通孔（TSV）。 使用粘合剂将分立的部件安装到临时载体上。 分立元件包括电容器。 使用模塑料封装IPD和分立组件。 在模塑料上形成第一金属层。 第一金属层连接到IPD的TSV并形成电感器。 去除临时载体和粘合剂，并且在IPD和分立组件上形成第二金属层。 第二金属层将IPD和分立元件互连并形成电感器。 在第二金属层上形成可选的互连结构。