公开(公告)号：US20120074547A1

公开(公告)日：2012-03-29

申请号：US12890409

申请日：2010-09-24

申请人： Byung Tai Do ,  Reza Argenty Pagaila ,  Linda Pei Ee Chua ,  Arnel Senosa Trasporto

发明人： Byung Tai Do ,  Reza Argenty Pagaila ,  Linda Pei Ee Chua ,  Arnel Senosa Trasporto

IPC分类号： H01L23/14 ,  H01L21/60

CPC分类号： H01L21/4832 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a hole in a lead body top side and a lead ridge protruding from a lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming a fill layer within the hole.

摘要翻译： 一种集成电路封装系统的制造方法，包括：形成封装焊盘; 在所述封装焊盘附近形成引线，所述引线在引线主体顶侧具有孔和从引线非水平侧突出的引线脊; 在封装桨上安装集成电路; 将电连接器连接到引线和集成电路; 并在孔内形成填充层。

公开(公告)号：US08138024B2

公开(公告)日：2012-03-20

申请号：US12037774

申请日：2008-02-26

申请人： Byung Tai Do ,  Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Byung Tai Do ,  Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L21/56 ,  H01L23/552

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method of manufacturing a package system includes: providing a semiconductor die with a contact pad and a ground pad, mounting the semiconductor die on a package substrate using and adhesive layer, forming a vertical conductive structure on top of the ground pad in the semiconductor die, encapsulating at least portions of the semiconductor die, the vertical conductive structure, and the package substrate using an encapsulant, covering at least portions of the encapsulant and the vertical conductive structure with a shielding layer to place the vertical conductive structure in electrical contact with the shielding layer, and connecting the shielding layer to the package substrate.

摘要翻译： 制造封装系统的方法包括：提供具有接触焊盘和接地焊盘的半导体管芯，使用粘合剂层将半导体管芯安装在封装衬底上，在半导体管芯中的接地焊盘顶部形成垂直导电结构 ，使用密封剂封装半导体管芯，垂直导电结构和封装衬底的至少一部分，用屏蔽层覆盖至少一部分密封剂和垂直导电结构，以使垂直导电结构与 屏蔽层，并且将屏蔽层连接到封装基板。

公开(公告)号：US08129231B2

公开(公告)日：2012-03-06

申请号：US12563928

申请日：2009-09-21

申请人： Seng Guan Chow ,  Oh Sug Kim ,  Byung Tai Do

发明人： Seng Guan Chow ,  Oh Sug Kim ,  Byung Tai Do

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.

摘要翻译： 半导体封装可以包括附接到衬底的管芯堆叠，其中接合线电连接两者。 通常，多个管芯堆叠被粘附到单个衬底上，使得可以一次制造几个半导体封装。 模制复合流量控制器在一个或多个不同位置处与衬底或半导体封装最佳地相关联。 流动控制器可以在封装过程中控制或引导模塑料的流动。 流量控制器的尺寸，形状和位置可以平滑模制化合物的流动，从而在含有模具的基材的区域和没有模具的基材的超过区域上流动的速度基本相当。 以这种方式，在封装期间可以基本上避免诸如封装，电线清扫和电线短路之类的缺陷的缺陷。

公开(公告)号：US20120034777A1

公开(公告)日：2012-02-09

申请号：US13273537

申请日：2011-10-14

申请人： Reza A. Pagaila ,  Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Byung Tai Do

发明人： Reza A. Pagaila ,  Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Byung Tai Do

IPC分类号： H01L21/768

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/12 ,  H01L24/13 ,  H01L24/19 ,  H01L24/25 ,  H01L24/28 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/24011 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/82039 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/83005

摘要： A semiconductor package includes a semiconductor wafer having a plurality of semiconductor die. A contact pad is formed over and electrically connected to an active surface of the semiconductor die. A gap is formed between the semiconductor die. An insulating material is deposited in the gap between the semiconductor die. An adhesive layer is formed over a surface of the semiconductor die and the insulating material. A via is formed in the insulating material and the adhesive layer. A conductive material is deposited in the via to form a through hole via (THV). A conductive layer is formed over the contact pad and the THV to electrically connect the contact pad and the THV. The plurality of semiconductor die is singulated. The insulating material can include an organic material. The active surface of the semiconductor die can include an optical device.

摘要翻译： 半导体封装包括具有多个半导体管芯的半导体晶片。 接触垫形成在半导体管芯的有源表面上并电连接到半导体管芯的有源表面。 在半导体管芯之间形成间隙。 绝缘材料沉积在半导体管芯之间的间隙中。 在半导体管芯和绝缘材料的表面上形成粘合剂层。 在绝缘材料和粘合剂层中形成通孔。 导电材料沉积在通孔中以形成通孔（THV）。 在接触焊盘和THV上形成导电层，以电连接接触焊盘和THV。 多个半导体管芯被切割。 绝缘材料可以包括有机材料。 半导体管芯的有源表面可以包括光学器件。

公开(公告)号：US20120032315A1

公开(公告)日：2012-02-09

申请号：US13197070

申请日：2011-08-03

申请人： Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

发明人： Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L21/4832 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有单个整体结构的封装桨，其中桨叶中心部分由桨周边部分包围; 形成邻近包装桨的端子; 在所述桨叶中心部分上安装集成电路; 并且在集成电路和端子上形成封装，该封装不会直接在桨周边部分上的封装分层。

公开(公告)号：US08097490B1

公开(公告)日：2012-01-17

申请号：US12870696

申请日：2010-08-27

申请人： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

发明人： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC分类号： H01L21/00 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L23/5386 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/83 ,  H01L2924/00012

摘要： A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.

公开(公告)号：US08084302B2

公开(公告)日：2011-12-27

申请号：US12044803

申请日：2008-03-07

申请人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

发明人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

IPC分类号： H01L23/485

CPC分类号： H01L24/19 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps.

摘要翻译： 通过在牺牲衬底上形成第一导电层，将半导体管芯安装到牺牲衬底上，在半导体管芯和第一导电层上方沉积绝缘层，暴露半导体管芯上的第一导电层和接触焊盘来制造半导体晶片 在所述第一导电层和所述接触焊盘之间的所述绝缘层上方形成第二导电层，在所述第二导电层上形成焊料凸点，在所述半导体管芯上方沉积密封剂，所述第一导电层和互连结构， 形成密封剂以暴露导电层和半导体管芯。 去除一部分密封剂以露出焊料凸块的一部分。 焊料凸块的尺寸设计成使得每个焊料凸块在封装体外均延伸。 通过电连接焊料凸块来堆叠半导体管芯。

公开(公告)号：US08062929B2

公开(公告)日：2011-11-22

申请号：US12788785

申请日：2010-05-27

申请人： Byung Tai Do ,  Heap Hoe Kuan ,  Seng Guan Chow

发明人： Byung Tai Do ,  Heap Hoe Kuan ,  Seng Guan Chow

IPC分类号： H01L21/00 ,  H01L23/02 ,  H01L23/06 ,  H01L23/12 ,  H01L23/053 ,  H01L23/34 ,  H01L23/04 ,  H01L23/13 ,  H01L23/31

CPC分类号： H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49805 ,  H01L23/5389 ,  H01L24/25 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a plurality of similar sized semiconductor die each with a plurality of bond pads formed over a surface of the semiconductor die. An insulating layer is formed around a periphery of each semiconductor die. A plurality of conductive THVs is formed through the insulating layer. A plurality of conductive traces is formed over the surface of the semiconductor die electrically connected between the bond pads and conductive THVs. The semiconductor die are stacked to electrically connect the conductive THVs between adjacent semiconductor die. The stacked semiconductor die are mounted within an integrated cavity of a substrate or leadframe structure. An encapsulant is deposited over the substrate or leadframe structure and the semiconductor die. A thermally conductive lid is formed over a surface of the substrate or leadframe structure. The stacked semiconductor die are attached to the thermally conductive lid.

摘要翻译： 半导体器件具有多个相似尺寸的半导体管芯，每个半导体管芯均具有在半导体管芯的表面上形成的多个接合焊盘。 在每个半导体管芯的周围形成绝缘层。 通过绝缘层形成多个导电THV。 在连接在接合焊盘和导电THV之间的半导体管芯的表面上形成多个导电迹线。 堆叠半导体管芯以将相邻半导体管芯之间的导电THV电连接。 堆叠的半导体管芯安装在衬底或引线框架结构的集成腔内。 在衬底或引线框架结构和半导体管芯上沉积密封剂。 导热盖形成在基板或引线框架结构的表面上。 堆叠的半导体管芯附接到导热盖。

公开(公告)号：US20110254173A1

公开(公告)日：2011-10-20

申请号：US13171341

申请日：2011-06-28

申请人： Byung Tai Do ,  Reza A. Pagaila

发明人： Byung Tai Do ,  Reza A. Pagaila

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed on the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be stacked and electrically interconnected through the TSVs.

摘要翻译： 半导体晶片具有由周边区域分离的多个半导体管芯。 在晶片的周边区域形成沟槽。 在管芯上形成通孔。 沟槽延伸到并且与通孔连续。 第一导电层沉积在沟槽和通孔中以形成导电TSV。 第一导电层被保形地施加或完全填充沟槽和通孔。 沟槽具有比加速第一导电层的形成的通孔更大的面积。 第二导电层沉积在管芯的前表面上。 第二导电层电连接到第一导电层。 第一和第二导电层可以同时形成。 去除晶片的后表面的一部分以露出第一导电层。 模具可以通过TSV堆叠和电互连。

公开(公告)号：US20110121295A1

公开(公告)日：2011-05-26

申请号：US13019643

申请日：2011-02-02

申请人： Francis Heap Hoe Kuan ,  Byung Tai Do ,  Lee Huang Chew

发明人： Francis Heap Hoe Kuan ,  Byung Tai Do ,  Lee Huang Chew

IPC分类号： H01L23/488

CPC分类号： H01L24/13 ,  H01L22/34 ,  H01L24/11 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/05552

摘要： A semiconductor device includes a substrate having a first conductive layer disposed on a top surface of the substrate. A first insulation layer is formed over the substrate and contacts a sidewall of the first conductive layer. A second conductive layer is formed over the first insulation layer. The second conductive layer includes a first portion disposed over the first conductive layer and a second portion that extends beyond an end of the first conductive layer. A second insulation layer is formed over the second conductive layer. A first opening in the second insulation layer exposes the first portion of the second conductive layer. A second opening in the second insulation layer away from the first opening exposes the second portion of the second conductive layer. The second insulation layer is maintained around the first opening. A conductive bump is formed over the first portion of the second conductive layer.

摘要翻译： 半导体器件包括具有设置在衬底顶表面上的第一导电层的衬底。 第一绝缘层形成在衬底上并与第一导电层的侧壁接触。 在第一绝缘层上形成第二导电层。 第二导电层包括设置在第一导电层上的第一部分和延伸超出第一导电层的端部的第二部分。 在第二导电层上形成第二绝缘层。 第二绝缘层中的第一开口露出第二导电层的第一部分。 远离第一开口的第二绝缘层中的第二开口暴露第二导电层的第二部分。 第二绝缘层保持在第一开口周围。 导电凸块形成在第二导电层的第一部分之上。