公开(公告)号：US20170222845A1

公开(公告)日：2017-08-03

申请号：US15400647

申请日：2017-01-06

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Bruno W. Garlepp ,  Pak S. Chau ,  Kevin S. Donnelly ,  Mark A. Horowitz ,  Stefanos Sidiropoulos ,  Billy W. Garrett ,  Carl W. Werner

IPC: H04L25/49 ,  H04L25/02 ,  G11C8/10 ,  G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  H04L25/03 ,  H04L7/033

CPC classification number: H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

Abstract: An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than 1, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver sub-circuit, to reduce gds distortion in the signal.

公开(公告)号：US20170214515A1

公开(公告)日：2017-07-27

申请号：US15369806

申请日：2016-12-05

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jared L. Zerbe ,  Carl William Werner

IPC: H04L7/027 ,  H03L7/081 ,  H04L7/00 ,  H04L7/033 ,  H03L7/091

CPC classification number: H04L7/0278 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337 ,  H04L7/0338

Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

公开(公告)号：US20170192912A1

公开(公告)日：2017-07-06

申请号：US15424714

申请日：2017-02-03

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/06 ,  G06F1/10 ,  G11C7/22

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US20170031864A1

公开(公告)日：2017-02-02

申请号：US15228614

申请日：2016-08-04

Applicant: Rambus Inc.

Inventor： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/364

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract translation: 集成电路装置包括具有输出驱动器的发送器电路。 集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。 集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。 集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

公开(公告)号：US09344074B2

公开(公告)日：2016-05-17

申请号：US14565802

申请日：2014-12-10

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

IPC: H03K5/13 ,  H03L7/06 ,  H03L7/099 ,  H03K5/00 ,  H03L7/16

CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

公开(公告)号：US09299408B2

公开(公告)日：2016-03-29

申请号：US14050107

申请日：2013-10-09

Applicant: Rambus Inc.

Inventor： Brian Hing-Kit Tsang ,  Jared L. Zerbe

IPC: G11C11/16 ,  G11C8/18 ,  H03L7/00 ,  G11C7/10 ,  G11C7/22 ,  H01L43/08 ,  G11C11/15

CPC classification number: H03K5/133 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/15 ,  G11C11/16 ,  H01L43/08 ,  H03K3/0315 ,  H03K7/06 ,  H03K2005/00019 ,  H03L7/00 ,  Y02D10/14

Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.

Abstract translation: 描述用于传达信息的方法和装置。 在一些实施例中，第一集成电路（IC）向第二IC提供时钟信号和数据信号，其中数据信号的数据位根据时钟信号定时，并且其中时钟信号的频率能够 甚至当数据信号有效时也被改变。

公开(公告)号：US20160043861A1

公开(公告)日：2016-02-11

申请号：US14820266

申请日：2015-08-06

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jared L. Zerbe ,  Carl William Werner

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0278 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337 ,  H04L7/0338

Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

公开(公告)号：US20160026599A1

公开(公告)日：2016-01-28

申请号：US14875433

申请日：2015-10-05

Applicant: Rambus Inc.

Inventor： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC: G06F13/42 ,  G06F12/02 ,  G06F13/40 ,  G11C16/32

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract translation: 集成电路装置包括具有输出驱动器的发送器电路。 集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。 集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。 集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

公开(公告)号：US20150319016A1

公开(公告)日：2015-11-05

申请号：US14683081

申请日：2015-04-09

Applicant: Rambus Inc.

Inventor： Vladimir M. Stojanovic ,  Andrew C. Ho ,  Anthony Bessios ,  Bruno W. Garlepp ,  Grace Tsang ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Jason C. Wei

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

Abstract translation: 描述信令系统。 信令系统包括发送设备，包括部分响应接收电路的接收设备以及耦合发送设备和接收设备的信令路径。 接收设备观察来自信令路径的均衡信号，并且包括使用来自最近先前解析的符号的反馈来采样当前输入符号的电路。 发送装置通过基于与最近先前分辨的符号值不相关的一个或多个数据值应用加权来均衡发送数据以发送均衡信号。

公开(公告)号：US08896355B1

公开(公告)日：2014-11-25

申请号：US14172031

申请日：2014-02-04

Applicant: Rambus Inc.

Inventor： Yue Lu ,  Jared L. Zerbe

IPC: H03B19/00 ,  H03L7/08

CPC classification number: H03K5/00006 ,  H03J2200/10 ,  H03L7/0802 ,  H03L7/083 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/16 ,  H03L7/24 ,  H04L7/033

Abstract: A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies.

Abstract translation: 在频率比较间隔期间比较可变频率输入时钟信号和参考时钟信号，以产生指示其频率比率的值。 然后应用频率比值来配置宽范围的锁频振荡器，以便在输入频率范围变窄的情况下工作。 由于变窄的输入频率范围针对输入时钟频率，因此宽频振荡器能够快速锁定到输入时钟频率的倍数。 因为频率比较间隔也是短暂的，所以在相对宽的输入时钟频率范围内可以实现非常快速锁定的时钟相乘操作。