公开(公告)号：US07649749B2

公开(公告)日：2010-01-19

申请号：US11822599

申请日：2007-07-09

申请人： Jun Tsukano ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

发明人： Jun Tsukano ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

IPC分类号： H05K1/11 ,  H05K1/14

CPC分类号： H05K1/0271 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/09018 ,  H05K2201/09481 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film. The second interconnection is connected to the first interconnection via the via. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, with a warped shape such that when the wiring substrate rests on a horizontal plate, at least a central part of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised.

摘要翻译： 布线基板包括基底绝缘膜，形成在基底绝缘膜的顶表面侧的第一互连，设置在形成在基底绝缘膜中的通孔中的通孔导体，以及设置在基底绝缘膜的底表面侧的第二互连 基底绝缘膜。 第二互连通过通孔连接到第一互连。 布线基板包括分开的基板单元区域，其中形成有第一互连，通孔和第二互连。 布线基板包括在基底绝缘膜上的翘曲控制图案，具有翘曲形状，使得当布线基板搁置在水平板上时，基板的平面的至少中心部分接触水平板，两者 一边抬起头。

公开(公告)号：US20090046441A1

公开(公告)日：2009-02-19

申请号：US12160132

申请日：2006-12-20

申请人： Takuo Funaya ,  Hideya Murai ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hirokazu Honda ,  Shinichi Miyazaki

发明人： Takuo Funaya ,  Hideya Murai ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hirokazu Honda ,  Shinichi Miyazaki

IPC分类号： H05K1/11 ,  H05K1/18

CPC分类号： H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19041 ,  H05K1/115 ,  H05K1/117 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/0272 ,  H05K2201/0352 ,  H05K2201/09845 ,  H05K2201/09972 ,  H05K2203/0425 ,  H05K2203/061 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wiring board for mounting semiconductor device, includes at least a dielectric film 1; wirings formed in the dielectric film 1; a plurality of electrode pads provided at front and back surfaces of the dielectric film with their surfaces exposed and at least portions of lateral sides of them buried into the dielectric film; vias connecting the wirings and the electrode pads. At least one via connecting each other the wirings formed in the dielectric film includes second material different from first material forming the vias connecting the wirings and the electrode pads. The wiring board for mounting semiconductor device, is effective for an increase in terminals and finer pitch of terminal intervals due to an improvement in integration, performance or multi-function of semiconductor devices, can mount semiconductor devices especially on both sides of the board at a high density and high accuracy, and furthermore, is excellent in reliability as well.

摘要翻译： 一种用于安装半导体器件的布线板，至少包括电介质膜1; 电介质膜1中形成的布线; 多个电极焊盘，其设置在电介质膜的前表面和后表面，其表面暴露，并且其侧面的至少一部分埋入电介质膜中; 连接布线和电极垫的通孔。 至少一个彼此连接的通孔形成在电介质膜中的布线包括与形成连接布线和电极焊盘的通孔的第一材料不同的第二材料。 用于安装半导体器件的布线板，由于半导体器件的集成度，性能或多功能性的提高，端子间距的增加和端子间隔的更细的间距是有效的，所以可以在半导体器件的两侧特别地安装半导体器件 高密度和高精度，此外，也具有优异的可靠性。

公开(公告)号：US20090026636A1

公开(公告)日：2009-01-29

申请号：US12178683

申请日：2008-07-24

申请人： Hideya MURAI ,  Kentaro Mori ,  Shintaro Yamamichi ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

发明人： Hideya MURAI ,  Kentaro Mori ,  Shintaro Yamamichi ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L23/544 ,  H01L23/5389 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  Y10T29/49146

摘要： Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.

摘要翻译： 半导体器件具有嵌入绝缘层中的半导体芯片。 半导体器件包括形成为具有外部连接焊盘的半导体芯片和用于通孔形成的定位标记; 包含非感光性树脂作为成分并具有多个通孔的绝缘层; 以及通过通路与外部连接焊盘电连接的布线，其至少一部分形成在绝缘层上。 绝缘层形成为在定位标记上方的部分具有凹部。 凹槽的底部是单独的绝缘层。 通孔相对于标记具有高位置精度。

公开(公告)号：US20060192287A1

公开(公告)日：2006-08-31

申请号：US11341445

申请日：2006-01-30

申请人： Kenta Ogawa ,  Jun Tsukano ,  Takehiko Maeda ,  Tadanori Shimoto ,  Shintaro Yamamichi ,  Kazuhiro Baba

发明人： Kenta Ogawa ,  Jun Tsukano ,  Takehiko Maeda ,  Tadanori Shimoto ,  Shintaro Yamamichi ,  Kazuhiro Baba

IPC分类号： H01L23/52

CPC分类号： H05K3/205 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511 ,  H05K1/113 ,  H05K3/107 ,  H05K3/4682 ,  H05K2201/09472 ,  H05K2201/096 ,  H05K2203/0384 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate comprises a first interconnection pattern formed of the first interconnection which comprises at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.

摘要翻译： 互连基板设置有在底面具有下沉部分的基底绝缘膜，设置在凹陷部分中的第一互连，形成在基底绝缘膜中的通孔，以及连接到第一互连件的第二互连 通过所述通孔内的导体，并形成在所述基底绝缘膜的顶表面上，其中所述互连衬底包括由所述第一互连形成的第一互连图案，所述第一互连图案至少包括沿着与第一互连正交的第二方向延伸的线状图案 第一方向和翘曲控制图案，其设置在基底绝缘膜的底面的下沉部分中，并且形成为抑制互连基板朝向底部绝缘膜两侧的底侧的翘曲 第一个方向

公开(公告)号：US20050051824A1

公开(公告)日：2005-03-10

申请号：US10967436

申请日：2004-10-18

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L27/04 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/00 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2，（Zr x，Hf 1-x）O 2（0

公开(公告)号：US06703705B2

公开(公告)日：2004-03-09

申请号：US09996054

申请日：2001-11-28

申请人： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

发明人： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

IPC分类号： H01L2352

CPC分类号： H01L24/81 ,  H01L23/50 ,  H01L23/642 ,  H01L24/73 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

摘要翻译： 半导体器件具有在电路形成面的周边部分设置有多个电源线连接焊盘和接地线连接焊盘的LSI器件，电连接到每个焊盘并粘附到LSI的金属箔引线5 通过绝缘层的器件，以及安装在金属箔引线的一个表面上的去耦电容器。

公开(公告)号：US5943547A

公开(公告)日：1999-08-24

申请号：US926369

申请日：1997-09-09

申请人： Shintaro Yamamichi ,  Pierre Yves Lesaicherre

发明人： Shintaro Yamamichi ,  Pierre Yves Lesaicherre

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/55

摘要： In a capacitor including a silicon substrate and an insulating layer formed on the silicon substrate having a contact hole, a lower electrode layer including a silicon diffusion preventing conductive layer and an oxidation resistance conductive layer, an upper electrode layer, and a high dielectric constant layer therebetween, the silicon diffusion preventing layer is located on or within the contact hole and is isolated from the high dielectric constant layer. The high dielectric constant layer is formed on an upper surface and a side surface of the oxidation resistance conductive layer.

摘要翻译： 在包括硅衬底和形成在具有接触孔的硅衬底上的绝缘层的电容器中，包括防硅扩散导电层和抗氧化电阻导电层的下电极层，上电极层和高介电常数层 其间，硅扩散防止层位于接触孔的上方或内部，并与高介电常数层隔离。 高介电常数层形成在抗氧化导电层的上表面和侧表面上。

公开(公告)号：US08975150B2

公开(公告)日：2015-03-10

申请号：US13190052

申请日：2011-07-25

申请人： Kentaro Mori ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

发明人： Kentaro Mori ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

IPC分类号： H01L21/76 ,  H01L21/683 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00

CPC分类号： H01L21/6835 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L2221/68345 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15174 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  Y10S438/977 ,  H01L2924/00

摘要： A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

摘要翻译： 透明板位于设置有定位标记的支撑板上，并且设置有释放材料。 然后将半导体元件定位成使得电极元件面向上，然后移除支撑板。 然后在剥离材料上形成绝缘树脂以覆盖半导体元件; 然后形成通孔，布线层，绝缘层，外部端子和阻焊剂。 然后透明板通过使用释放材料从半导体器件剥离。 因此，可以高精度地安装芯片，在制造过程中不需要在将芯片安装在基板上时提供定位标记，并且可以容易地去除基板。 结果，可以以低成本制造具有高密度和薄型的半导体器件。

公开(公告)号：US08766440B2

公开(公告)日：2014-07-01

申请号：US13582128

申请日：2011-01-25

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima

IPC分类号： H01L23/52

CPC分类号： H05K1/186 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/23 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H05K3/4644 ,  H01L2924/00

摘要： A wiring board including a built-in semiconductor element includes the semiconductor element, a peripheral insulating layer covering an outer peripheral side surface of the semiconductor element, an upper surface-side wiring provided on an upper surface side of the wiring board, and a lower surface-side wiring provided on a lower surface side of the wiring board. The semiconductor element includes a first wiring structure layer including a first wiring and a first insulating layer alternately provided on a semiconductor substrate, and a second wiring structure layer including a second wiring and a second insulating layer alternately provided on the first wiring structure layer. The upper surface-side wiring includes a wiring electrically connected to the first wiring via the second wiring. The second wiring is thicker than the first wiring and thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer.

摘要翻译： 包括内置半导体元件的布线板包括半导体元件，覆盖半导体元件的外周侧表面的外围绝缘层，设置在布线基板的上表面侧的上表面侧布线，以及下部 设置在布线基板的下表面侧的表面侧配线。 半导体元件包括：第一布线结构层，包括交替设置在半导体基板上的第一布线和第一绝缘层;以及第二布线结构层，包括交替设置在第一布线结构层上的第二布线和第二绝缘层。 上表面侧布线包括经由第二布线电连接到第一布线的布线。 第二布线比第一布线厚，比上表面布线薄。 第二绝缘层由树脂材料形成，并且比第一绝缘层厚。

公开(公告)号：US08710669B2

公开(公告)日：2014-04-29

申请号：US13320798

申请日：2010-05-18

申请人： Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

发明人： Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/10674 ,  H01L2924/00

摘要： A semiconductor device includes a core substrate, and at least one insulating layer and at least one wiring layer that are disposed on a first surface and a second, opposite surface of the substrate. The semiconductor device includes a via disposed in the insulating layer and in the core substrate, and which connects the wiring layers to one another. The semiconductor device includes a semiconductor element mounted on the first surface, forming an electrode terminal that faces up. The semiconductor device includes a connecting portion that penetrates the insulating layer and directly connects the electrode terminal of the semiconductor element and the wiring layer on the first surface. A minimum wiring pitch of this wiring that of any wiring layer on the second surface.

摘要翻译： 半导体器件包括芯基板，以及设置在基板的第一表面和第二相对表面上的至少一个绝缘层和至少一个布线层。 半导体器件包括布置在绝缘层和芯基板中并且将布线层彼此连接的通孔。 半导体器件包括安装在第一表面上的半导体元件，形成面向上的电极端子。 半导体器件包括穿透绝缘层并直接连接半导体元件的电极端子和第一表面上的布线层的连接部分。 该布线的最小布线间距为第二面上任何布线层的布线间距。