公开(公告)号：US08637350B2

公开(公告)日：2014-01-28

申请号：US13439447

申请日：2012-04-04

Applicant: Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

Inventor： Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

IPC: H01L21/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract translation: 一种制造芯片堆叠的半导体封装的方法，所述方法包括制备包括多个第一芯片的基片，每个第一芯片均具有穿硅通孔（TSV）; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。

公开(公告)号：US08592991B2

公开(公告)日：2013-11-26

申请号：US13235369

申请日：2011-09-17

Applicant: Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

Inventor： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/00

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract translation: 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。

公开(公告)号：US08362621B2

公开(公告)日：2013-01-29

申请号：US12393109

申请日：2009-02-26

Applicant: Ho Jin Lee ,  Dong Hyeon Jang ,  Nam Seog Kim ,  In Young Lee ,  Ha Young Yim

Inventor： Ho Jin Lee ,  Dong Hyeon Jang ,  Nam Seog Kim ,  In Young Lee ,  Ha Young Yim

IPC: H01L23/522 ,  H01L25/11

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01055 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941

Abstract: A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.

Abstract translation: 微电子结构包括在衬底上的导电焊盘。 导电垫包括延伸穿过其中的第一和第二开口。 导电焊盘上的第一导电通孔延伸穿过导电焊盘中的第一开口进入衬底。 邻近第一导电通孔的导电焊盘上的第二导电通孔延伸穿过导电焊盘中的第二开口进入衬底。 导电通孔中的至少一个可以与导电焊盘电绝缘。 还讨论了相关设备和制造方法。

公开(公告)号：US20120292195A1

公开(公告)日：2012-11-22

申请号：US13438020

申请日：2012-04-03

Applicant: Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

Inventor： Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

IPC: C25B15/00 ,  C25B9/00

CPC classification number: C25D17/001 ,  C25D5/02 ,  C25D5/08 ,  C25D7/123 ,  C25D17/008 ,  H01L21/2885

Abstract: An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution.

Abstract translation: 一种用于电镀半导体器件的设备包括一个容纳电镀溶液的电镀液和一个在电镀槽中的一个电极板，该电极板包括多个孔，该多个孔被配置成将电镀液通过桨向衬底通过，电镀液流动加强 所述部分被配置为选择性地将所述电镀溶液的流动加强到所述基板的预定区域，所述基板的所述预定区域是需要相对增加所述电镀液的金属离子供应的区域。

公开(公告)号：US08119448B2

公开(公告)日：2012-02-21

申请号：US12817304

申请日：2010-06-17

Applicant: Son-Kwan Hwang ,  In-Young Lee ,  Ho-Jin Lee ,  Dong-Hyeon Jang

Inventor： Son-Kwan Hwang ,  In-Young Lee ,  Ho-Jin Lee ,  Dong-Hyeon Jang

IPC: H01L21/00

CPC classification number: H01L24/11 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/9201 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10329 ,  H01L2224/05552

Abstract: A semiconductor chip comprises a substrate including a front surface and a rear surface, the substrate having a first via hole formed in the front surface and a second via hole formed in the rear surface, a first conductive plug formed on the substrate, the first conductive plug including a first portion formed in the first via hole and a second portion protruding from the front surface of the substrate, and a second conductive plug formed on the first conductive plug, the second conductive plug having a smaller cross-sectional area than the first conductive plug.

Abstract translation: 一种半导体芯片，包括：具有前表面和后表面的基板，所述基板具有形成在所述前表面上的第一通孔和形成在所述后表面中的第二通孔，形成在所述基板上的第一导电塞，所述第一导电 所述插头包括形成在所述第一通孔中的第一部分和从所述基板的前表面突出的第二部分，以及形成在所述第一导电插塞上的第二导电插塞，所述第二导电插塞具有比所述第一通孔更小的横截面积 导电插头

公开(公告)号：US08110922B2

公开(公告)日：2012-02-07

申请号：US12588231

申请日：2009-10-08

Applicant: Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.

Abstract translation: 晶片级半导体模块可以包括安装在模块板上的模块板和IC芯片组。 IC芯片组可以包括在相邻IC芯片之间具有划线区域的多个IC芯片。 每个IC芯片可以具有具有多个芯片焊盘和后表面的有源表面的半导体衬底。 可以在每个IC芯片的半导体衬底的有源表面上提供钝化层，并且可以具有可以暴露芯片焊盘的开口。 密封部分可以形成在划线区域中。

公开(公告)号：US07592709B2

公开(公告)日：2009-09-22

申请号：US11430900

申请日：2006-05-10

Applicant: Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

Inventor： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/28

CPC classification number: H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

Abstract translation: 球栅阵列型片上芯片封装可以包括具有支撑多个接触焊盘的有源表面的集成电路芯片。 插入器可以粘附到集成电路芯片的有源表面。 可以通过插入件提供至少一个孔以暴露接触垫。 可以具有支撑多个金属线的第一表面的板可以具有粘附到插入件的第二表面。 板可以具有开口，接触垫可以穿过该开口露出。 多个接合线可以通过开口将接触垫连接到金属线。

公开(公告)号：US20090184411A1

公开(公告)日：2009-07-23

申请号：US12353501

申请日：2009-01-14

Applicant: Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

Inventor： Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

IPC: H01L23/48

CPC classification number: H01L24/91 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

Abstract translation: 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括衬底，其包括芯片焊盘，电连接到芯片焊盘并且包括开口的再分布线。 半导体封装还可以包括外部端子连接部分和设置在开口处并电连接到重新分配线路的外部端子连接焊盘。 本发明的总体构思可以解决包含在再分布线中的金的成分被阻止扩散到相邻的凸块焊盘中以形成空隙或不期望的金属间化合物的问题。 在片上芯片结构中，下部芯片的多个凸起连接到上部芯片以提高片上芯片结构的可靠性，分集性和功能性。

公开(公告)号：US20090020878A1

公开(公告)日：2009-01-22

申请号：US12014600

申请日：2008-01-15

Applicant: Seung-Kwan RYU ,  Hee-Kook CHOI ,  Sung-Min SIM ,  Dong-Hyeon JANG

Inventor： Seung-Kwan RYU ,  Hee-Kook CHOI ,  Sung-Min SIM ,  Dong-Hyeon JANG

IPC: H01L21/768 ,  H01L23/52

CPC classification number: H01L23/3114 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/30105

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device having a bonding pad and an interlayer insulating layer disposed on the semiconductor device. The interlayer insulating layer has an opening which exposes the bonding pad and has at least one cavity therein. A redistributed interconnection is disposed on the interlayer insulating layer and electrically connected to the exposed bonding pad. The redistributed interconnection is disposed over the cavity. A method of fabricating the semiconductor package is also provided.

Abstract translation: 提供半导体封装。 半导体封装包括具有接合焊盘和设置在半导体器件上的层间绝缘层的半导体器件。 层间绝缘层具有露出接合焊盘并且在其中具有至少一个空腔的开口。 重新分布的互连布置在层间绝缘层上并电连接到暴露的焊盘。 再分布的互连设置在空腔上。 还提供了制造半导体封装的方法。

公开(公告)号：US07307340B2

公开(公告)日：2007-12-11

申请号：US10824111

申请日：2004-04-14

Applicant: Seung Duk Baek ,  Dong Hyeon Jang ,  Gu Sung Kim ,  Kang Wook Lee ,  Jae Sik Chung

Inventor： Seung Duk Baek ,  Dong Hyeon Jang ,  Gu Sung Kim ,  Kang Wook Lee ,  Jae Sik Chung

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/34 ,  H01L25/10

CPC classification number: H01L23/5228 ,  H01L23/367 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic module comprises a monolithic microelectronic substrate including at least one integrated circuit die, e.g., a plurality of unseparated memory dice or a mixture of different types of integrated circuit dice. The monolithic substrate further includes a redistribution structure disposed on the at least one integrated circuit die and providing a connector contact coupled to the at least one integrated circuit die. For example, the connector contact may be configured as edge connector contact for the module. The redistribution structure may be configured to provide a passive electronic device, e.g., an inductor, capacitor and/or resistor, electrically coupled to the at least one integrated circuit die and/or the redistribution structure may comprise at least one conductive layer configured to provide electrical connection to a contact pad of an electronic device mounted on the substrate. Methods of fabricating electronic modules are also discussed.

Abstract translation: 电子模块包括单片微电子衬底，其包括至少一个集成电路管芯，例如多个未分离的存储器管芯或不同类型的集成电路管芯的混合。 整体式衬底还包括设置在至少一个集成电路管芯上的再分配结构，并提供耦合到至少一个集成电路管芯的连接器接头。 例如，连接器触点可以被配置为模块的边缘连接器触点。 再分配结构可以被配置为提供电耦合到至少一个集成电路管芯的无源电子器件，例如电感器，电容器和/或电阻器，和/或再分配结构可以包括至少一个导电层，其被配置为提供 电连接到安装在基板上的电子设备的接触焊盘。 还讨论了制造电子模块的方法。