公开(公告)号：US09418878B2

公开(公告)日：2016-08-16

申请号：US14340187

申请日：2014-07-24

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin

IPC: H01L21/44 ,  H01L23/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/68 ,  H01L23/28

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/68 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material.

Abstract translation: 半导体器件通过提供临时载体并提供具有在其有源表面上形成的多个凸起的半导体管芯制成。 粘合剂材料作为半导体管芯的载体或有源表面上的多个岛或凸起沉积。 粘合剂层也可以作为连续层沉积在模具的载体或活性表面上。 半导体管芯安装在载体上。 密封剂沉积在模具和载体上。 粘合剂材料在沉积密封剂的同时将半导体管芯保持在载体上。 在模具的有效表面上形成互连结构。 互连结构电连接到半导体管芯的凸点。 可以在形成互连结构之前去除粘合剂材料，或者可以在粘合剂材料上形成互连结构。

公开(公告)号：US20160197059A1

公开(公告)日：2016-07-07

申请号：US15069719

申请日：2016-03-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/552 ,  H01L25/50 ,  H01L27/016 ,  H01L27/0711 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2225/06531 ,  H01L2225/06537 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference.

Abstract translation: 半导体器件通过提供衬底制成，在衬底上形成第一绝缘层，在第一绝缘层上形成第一导电层，在第一导电层上形成第二绝缘层，并在第二绝缘层上形成第二导电层 绝缘层。 第二绝缘层，第一导电层和第二导电层的一部分形成集成的无源器件（IPD）。 IPD可以是电感，电容或电阻。 多个导电柱形成在第二导电层上。 一个导电柱从半导体器件中去除热量。 在IPD上并围绕多个导电柱形成第三绝缘层。 在IPD，第三绝缘层和导电柱上形成屏蔽层。 屏蔽层电连接到导电柱以屏蔽IPD免受电磁干扰。

公开(公告)号：US20160118332A1

公开(公告)日：2016-04-28

申请号：US14887561

申请日：2015-10-20

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L23/528 ,  H01L21/768 ,  H01L25/00 ,  H01L23/31 ,  H01L25/16 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/19105 ,  H01L2224/83

Abstract: A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU, and disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD. A resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：提供第一生产线，提供第二生产线，以及使用第一生产线形成第一再分布互连结构，同时使用第二生产线形成第二再分配互连结构。 该方法还包括以下步骤：测试第一再分布互连结构的第一单元以确定第一已知良好单元（KGU），在第一再分配互连结构的第一KGU上设置已知的良好半导体管芯（KGD），测试 确定第二重分布互连结构的单元，以确定第二已知良好单元（KGU，并且将第二再分布互连结构的第二KGU布置在第一再分配互连结构的第一KGU上，并且KGD），第二生产线的分辨率为 大于第一条生产线的分辨率。

公开(公告)号：US09318404B2

公开(公告)日：2016-04-19

申请号：US13759911

申请日：2013-02-05

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and offset from the semiconductor die. A portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface. The plurality of vias comprises a depth greater than a thickness of the portion of the encapsulant. A first portion of the plurality of vias is formed in a row offset from a side of the semiconductor die. A second portion of the plurality of vias is formed as an array of vias offset from a corner of the semiconductor die. A repair material disposed within the plurality of vias.

Abstract translation: 半导体器件包括半导体管芯。 密封剂设置在半导体管芯周围以形成周边区域。 在半导体管芯和密封剂的第一表面上形成互连结构。 多个通孔部分地通过密封剂的周边区域形成并偏离半导体管芯。 密封剂的一部分设置在与第一表面相对的半导体管芯的第二表面上。 多个通孔包括大于该密封剂部分的厚度的深度。 多个通路的第一部分形成为从半导体管芯的一侧偏移的行。 多个通孔的第二部分形成为从半导体管芯的拐角偏移的通孔阵列。 设置在多个通孔内的修补材料。

公开(公告)号：US09142428B2

公开(公告)日：2015-09-22

申请号：US14080609

申请日：2013-11-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Jose A. Caparas ,  Kang Chen ,  Hin Hwa Goh

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/28

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/00 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73259 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

Abstract translation: 半导体器件具有第一半导体管芯，其包括安装在具有热可释放层的载体上的TSV。 具有第一热膨胀系数CTE的第一密封剂沉积在第一半导体管芯上。 第一密封剂包括第一密封剂的周边中的升高部分，其减少翘曲。 暴露TSV的表面。 第二半导体管芯安装到TSV的表面，并在第一和第二半导体管芯之间形成间隙。 具有第二CTE的第二密封剂沉积在第一和第二半导体管芯上并且在间隙内。 第一个CTE大于第二个CTE。 在一个实施例中，第一和第二密封剂形成在追逐模具中。 在第一和第二半导体管芯上形成互连结构。

公开(公告)号：US20150259194A1

公开(公告)日：2015-09-17

申请号：US14643074

申请日：2015-03-10

Applicant: STATS ChipPAC, LTD.

Inventor： Yaojian Lin ,  Won Kyoung Choi ,  Kang Chen ,  Ivan Micallef

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00904 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/13091 ,  H01L2924/15 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

Abstract translation: 半导体器件具有与第一半导体管芯相邻的第一半导体管芯和模块化互连结构。 密封剂沉积在第一半导体管芯和模块化互连结构上，作为重构面板。 互连结构形成在第一半导体管芯和模块互连结构之上。 第一半导体管芯的有源区域没有互连结构。 第二半导体管芯安装在第一半导体管芯上，第二半导体管芯的有源表面朝向第一半导体管芯的有效表面。 复原的面板在安装第二半导体管芯之前或之后被分割。 第一或第二半导体管芯包括微机电系统（MEMS）。 第二半导体管芯包括密封剂和形成在第二半导体管芯上的互连结构。 或者，第二半导体管芯安装到设置在互连结构上的插入器。

公开(公告)号：US20150228552A1

公开(公告)日：2015-08-13

申请号：US14697352

申请日：2015-04-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/78 ,  H01L23/528

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US20150179481A1

公开(公告)日：2015-06-25

申请号：US14139312

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device includes a carrier and a plurality of semiconductor die disposed over the carrier. An encapsulant is deposited over the semiconductor die. A composite layer is formed over the encapsulant to form a panel. The carrier is removed. A conductive layer is formed over the panel. An insulating layer is formed over the conductive layer. The carrier includes a glass layer, a second composite layer formed over the glass layer, and an interface layer formed over the glass layer. The composite layer and encapsulant are selected to tune a coefficient of thermal expansion of the panel. The panel includes panel blocks comprising an opening separating the panel blocks. The encapsulant or insulating material is deposited in the opening. A plurality of support members are disposed around the panel blocks. An interconnect structure is formed over the conductive layer.

Abstract translation: 半导体器件包括载体和设置在载体上的多个半导体管芯。 密封剂沉积在半导体管芯上。 在密封剂上形成复合层以形成面板。 载体被移除。 导电层形成在面板上。 在导电层上形成绝缘层。 载体包括玻璃层，形成在玻璃层上的第二复合层和形成在玻璃层上的界面层。 选择复合层和密封剂来调节面板的热膨胀系数。 面板包括面板块，其包括分开面板块的开口。 密封剂或绝缘材料沉积在开口中。 多个支撑构件设置在面板块周围。 在导电层上形成互连结构。

公开(公告)号：US20150091145A1

公开(公告)日：2015-04-02

申请号：US14566870

申请日：2014-12-11

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76829 ,  H01L21/4832 ,  H01L21/486 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06182 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/20 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/185 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.

Abstract translation: 半导体器件具有安装在载体上的半导体管芯。 封装剂沉积在载体和半导体管芯上。 载体被移除。 在密封剂和模具的第一表面上形成第一互连结构。 在密封剂和模具的第二表面上形成第二互连结构。 在第一互连结构之上形成第一保护层，并且在形成通孔之前在第二互连结构上形成第二保护层。 通过第二互连结构，密封剂和第一互连结构形成多个通孔。 在通孔中形成第一导电层以电连接第一互连结构和第二互连结构。 绝缘层形成在第一互连结构和第二互连结构之上，并且形成在通孔中。 分立半导体部件可以安装到第一互连结构。

公开(公告)号：US08962476B2

公开(公告)日：2015-02-24

申请号：US13893616

申请日：2013-05-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Xia Feng ,  Jianmin Feng ,  Kang Chen

IPC: H01L21/31

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/525 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/0235 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/381 ,  H05K2201/09854 ,  H01L2924/01014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和第一导电层。 在半导体管芯的表面上形成第一绝缘层。 在第一绝缘层和第一导电层上形成第二绝缘层。 在第一导电层上的第二绝缘层中形成开口。 在第一导电层和第二绝缘层上的开口中形成第二导电层。 第二导电层的宽度小于沿着第一轴线的第一导电层的宽度。 第二导电层的宽度大于沿着垂直于第一轴线的第二轴线的第一导电层的宽度。 在第二导电层和第一绝缘层上形成第三绝缘层。