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    Package structure and method for forming the same
    82.
    发明授权
    Package structure and method for forming the same 有权

    公开(公告)号：US10128193B2

    公开(公告)日：2018-11-13

    申请号：US15413690

    申请日：2017-01-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Ching-Yao Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh

    IPC: H01L21/4763 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10

    Abstract: A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.

    Package structure and method for forming the same
    83.
    发明授权
    Package structure and method for forming the same 有权

    公开(公告)号：US10014260B2

    公开(公告)日：2018-07-03

    申请号：US15347912

    申请日：2016-11-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Da Tsai ,  Cheng-Ping Lin ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

    IPC: H01L23/552 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/29

    Abstract: Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method also includes forming a conductive layer over the carrier substrate. The method further includes forming a passivation layer over the conductive layer. The passivation layer includes openings that expose portions of the conductive layer. In addition, the method includes bonding integrated circuit dies to the portions of the conductive layer through bumps. There is a space between the integrated circuit dies and the passivation layer. The method also includes filling the space with a first molding compound. The first molding compound surrounds the bumps and the integrated circuit dies. The method further includes forming a second molding compound capping the first molding compound and the integrated circuit dies. The passivation layer has a sidewall that is covered by the second molding compound.

    Semiconductor device and method
    86.
    发明授权
    Semiconductor device and method 有权

    公开(公告)号：US12300580B2

    公开(公告)日：2025-05-13

    申请号：US18732879

    申请日：2024-06-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsu-Lun Liu ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chen-En Yen ,  Cheng-Lung Yang ,  Kuanchih Huang

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/60

    Abstract: Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the plurality of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.

    Metal bumps and method forming same
    88.
    发明授权
    Metal bumps and method forming same 有权

    公开(公告)号：US12230595B2

    公开(公告)日：2025-02-18

    申请号：US17333187

    申请日：2021-05-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Da Cheng ,  Yung-Ching Chao ,  Chun Kai Tzeng ,  Cheng Jen Lin ,  Chin Wei Kang ,  Yu-Feng Chen ,  Mirng-Ji Lii

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/488

    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

    PROCESS FOR TUNING VIA PROFILE IN DIELECTRIC MATERIAL
    90.
    发明申请
    PROCESS FOR TUNING VIA PROFILE IN DIELECTRIC MATERIAL 有权

    公开(公告)号：US20240371915A1

    公开(公告)日：2024-11-07

    申请号：US18777699

    申请日：2024-07-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun Kai Tzeng ,  Cheng Jen Lin ,  Yung-Ching Chao ,  Ming-Da Cheng ,  Mirng-Ji Lii

    IPC: H01L21/311 ,  H01L23/522

    Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

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