利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.044 秒)

    MANAGING INPUT/OUTPUT INTERRUPTIONS IN NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS, AND METHODS THEREFOR
    4.
    发明申请
    MANAGING INPUT/OUTPUT INTERRUPTIONS IN NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS, AND METHODS THEREFOR 有权
    管理非专用中断硬件环境中的输入/输出中断及其方法

    公开(公告)号：US20080046623A1

    公开(公告)日：2008-02-21

    申请号：US11851744

    申请日：2007-09-07

    申请人： Brenton Belmar ,  Janet Easton ,  Tan Lu ,  Damian Osisek ,  Richard Tarcza ,  Leslie Wyman

    发明人： Brenton Belmar ,  Janet Easton ,  Tan Lu ,  Damian Osisek ,  Richard Tarcza ,  Leslie Wyman

    IPC分类号： G06F13/24

    CPC分类号： G06F9/4812 ,  G06F9/45537

    摘要： Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

    摘要翻译： 输入/输出中断在不使用专用每个客户机中断硬件来呈现中断的计算环境中进行管理。 环境中可分派的访客程序直接接收I / O中断，无需管理程序干预。 这通过使用存储在存储器中并与每个客户程序相关联的一个或多个中断控制来促进。 对于目前不可分发的客户程序，可以为客人发布中断，并可以对通知程序进行汇总。 然后管理程序可以在单个调用中处理多个客人的多个通知。

    MANAGING INPUT/OUTPUT INTERRUPTIONS IN NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS
    5.
    发明申请
    MANAGING INPUT/OUTPUT INTERRUPTIONS IN NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS 有权
    管理非专用中断硬件环境中的输入/输出中断

    公开(公告)号：US20060242643A1

    公开(公告)日：2006-10-26

    申请号：US11428085

    申请日：2006-06-30

    申请人： Brenton Belmar ,  Janet Easton ,  Tan Lu ,  Damian Osisek ,  Richard Tarcza ,  Leslie Wyman

    发明人： Brenton Belmar ,  Janet Easton ,  Tan Lu ,  Damian Osisek ,  Richard Tarcza ,  Leslie Wyman

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4812 ,  G06F9/45537

    摘要： Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

    摘要翻译： 输入/输出中断在不使用专用每个客户机中断硬件来呈现中断的计算环境中进行管理。 环境中可分派的访客程序直接接收I / O中断，无需管理程序干预。 这通过使用存储在存储器中并与每个客户程序相关联的一个或多个中断控制来促进。 对于目前不可分发的客户程序，可以为客人发布中断，并可以对通知程序进行汇总。 然后管理程序可以在单个调用中处理多个客人的多个通知。

    System and method for alias mapping of address space
    6.
    发明申请
    System and method for alias mapping of address space 失效
    用于地址空间的别名映射的系统和方法

    公开(公告)号：US20070028072A1

    公开(公告)日：2007-02-01

    申请号：US11190224

    申请日：2005-07-26

    申请人： James Hennessy ,  William Holder ,  Damian Osisek

    发明人： James Hennessy ,  William Holder ,  Damian Osisek

    IPC分类号： G06F12/00

    CPC分类号： G06F12/109 ,  G06F12/126 ,  G06F2212/6042

    摘要： Mapping of address space by providing real storage including first and second address spaces. The second address space is smaller than and contained within the first address space. Provided within virtual storage is a system execution space. Providing within the system execution space is a system execution area having a size equal to or less than the second address space. The system execution area includes a control program having a first portion capable of addressing the first address space and the system execution space, a second portion constrained to address only the second address space and the system execution area, and at least one alias page. Responsive to a control program request for a first page in the virtual storage, a first frame is assigned in real storage corresponding to the page. Responsive to a request from the second portion of the control program for the first page, allocating an alias page in the system execution area, the alias page backed by the first frame.

    摘要翻译： 通过提供包括第一和第二地址空间的真实存储来映射地址空间。 第二地址空间小于并包含在第一地址空间内。 在虚拟存储中提供的是系统执行空间。 在系统执行空间内提供具有等于或小于第二地址空间的大小的系统执行区域。 系统执行区域包括具有能够寻址第一地址空间和系统执行空间的第一部分的控制程序，被限制为仅寻址第二地址空间和系统执行区域的第二部分以及至少一个别名页面。 响应于对虚拟存储器中的第一页的控制程序请求，在对应于页面的实际存储中分配第一帧。 响应于来自第一页面的控制程序的第二部分的请求，在系统执行区域中分配别名页面，由第一帧支持的别名页面。

    Memory mapped Input/Output virtualization
    7.
    发明申请
    Memory mapped Input/Output virtualization 有权
    内存映射输入/输出虚拟化

    公开(公告)号：US20050114586A1

    公开(公告)日：2005-05-26

    申请号：US10723405

    申请日：2003-11-25

    申请人： Frank Brice ,  Richard Errickson ,  Mark Farrell ,  Charles Gainey ,  Thomas Gregg ,  Carol Hernandez ,  Damian Osisek ,  Donald Schmidt

    发明人： Frank Brice ,  Richard Errickson ,  Mark Farrell ,  Charles Gainey ,  Thomas Gregg ,  Carol Hernandez ,  Damian Osisek ,  Donald Schmidt

    IPC分类号： G06F9/455 ,  G06F12/02 ,  G11C5/00

    CPC分类号： G06F12/0292 ,  G06F9/45537 ,  G06F2212/206

    摘要： A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with a definition of a z/Architecture; allocating at least one of a real resource and a virtual resource associated with the first alternate address space to a process; ensuring that the selected process corresponds with the process to which the resource is allocated. The process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.

    摘要翻译： 一种向备用地址空间执行存储器映射输入输出操作的方法，包括：根据z / Architecture的定义，建立指向与适配器相关联的第一存储器映射输入输出备用地址空间的第一指令以存储数据; 建立指向与适配器相关联的第一存储器映射输入输出交替地址空间的第二指令，以根据z / Architecture的定义加载数据; 将与所述第一替代地址空间相关联的实际资源和虚拟资源中的至少一个分配给进程; 确保所选择的进程与分配资源的进程相对应。 该过程发生第一指令和第二指令中的至少一个，从而导致使用第一替代地址空间执行存储和加载中的至少一个。

    System and method for testing for memory address aliasing errors
    8.
    发明申请
    System and method for testing for memory address aliasing errors 有权
    用于测试内存地址混叠错误的系统和方法

    公开(公告)号：US20070028075A1

    公开(公告)日：2007-02-01

    申请号：US11190710

    申请日：2005-07-26

    申请人： William Holder ,  Damian Osisek ,  Thomas Vail ,  Donald Wilton

    发明人： William Holder ,  Damian Osisek ,  Thomas Vail ,  Donald Wilton

    IPC分类号： G06F12/00

    CPC分类号： G11C29/02 ,  G11C29/024 ,  G11C29/025

    摘要： Aliasing errors, occasioned by including extra or missing bits, wrong addressing mode, or wrong address context, are detected by providing a storage configuration including gaps in valid addresses. An exception is thrown responsive to an address reference to a gap. Gaps are configured at complementary address ranges to facilitate detection of aliasing errors.

    摘要翻译： 通过提供包括有效地址间隙的存储配置来检测混淆错误，包括额外的或缺少的位，错误的寻址模式或错误的地址上下文。 响应于对间隙的地址引用而引发异常。 间隙配置在互补地址范围，以便于检测混叠误差。