公开(公告)号：US20220157682A1

公开(公告)日：2022-05-19

申请号：US17502082

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Edward FUERGUT ,  Chii Shang HONG ,  Teck Sim LEE ,  Bernd SCHMOELZER ,  Ke Yan TEAN ,  Lee Shuang WANG

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/56

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

公开(公告)号：US20140327003A1

公开(公告)日：2014-11-06

申请号：US13886283

申请日：2013-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Edward FUERGUT ,  Irmgard Escher-Poeppel ,  Manfred Engelhardt ,  Hans-Joerg Timme ,  Hannes Eder

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/24 ,  H01L21/568 ,  H01L21/67069 ,  H01L21/67253 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/784 ,  H01L22/12 ,  H01L22/26 ,  H01L22/30 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/94 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

Abstract translation: 提供一种处理在公共基板中彼此连接的多个封装电子芯片的方法，其中所述方法包括蚀刻所述电子芯片，检测指示在所述指示符的曝光之后至少部分移除指示符结构的信息 嵌入在电子芯片的至少一部分内并且在蚀刻之后暴露出指示器结构之上的芯片材料的结构，以及在检测到指示结构的至少部分移除的信息时调整处理。

公开(公告)号：US20240395646A1

公开(公告)日：2024-11-28

申请号：US18792129

申请日：2024-08-01

Applicant: Infineon Technologies AG

Inventor： Edward FUERGUT ,  Chii Shang HONG ,  Teck Sim LEE ,  Bernd SCHMOELZER ,  Ke Yan TEAN ,  Lee Shuang WANG

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

公开(公告)号：US20240038612A1

公开(公告)日：2024-02-01

申请号：US18380276

申请日：2023-10-16

Applicant: Infineon Technologies AG

Inventor： Edward FUERGUT ,  Chii Shang HONG ,  Teck Sim LEE ,  Bernd SCHMOELZER ,  Ke Yan TEAN ,  Lee Shuang WANG

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3121 ,  H01L23/49555 ,  H01L23/49537 ,  H01L21/56 ,  H01L23/49568 ,  H01L23/49541 ,  H01L24/46 ,  H01L24/83 ,  H01L23/49506 ,  H01L23/49551 ,  H01L23/49838 ,  H01L24/49 ,  H01L23/49503 ,  H01L23/49575 ,  H01L2924/181

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

公开(公告)号：US20230064442A1

公开(公告)日：2023-03-02

申请号：US17879900

申请日：2022-08-03

Applicant: Infineon Technologies AG

Inventor： Chan Whai Augustine KAN ,  Martin MAYER ,  Edmund RIEDL ,  Edward FUERGUT ,  Harry Walter SAX

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/42 ,  H01L23/00

Abstract: A chip package structure is disclosed. In one example, the chip package may include a chip, an encapsulation material, and an exposed pad that is electrically conductively connected to the chip. A layer of a porous or dendrite-comprising adhesion promoter is on a surface of the exposed pad. A thermal interface material that is attached to the exposed pad by the layer.

公开(公告)号：US20170221857A1

公开(公告)日：2017-08-03

申请号：US15422674

申请日：2017-02-02

Applicant: Infineon Technologies AG

Inventor： Joachim MAHLER ,  Edward FUERGUT ,  Georg MEYER-BERG

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/96 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3157 ,  H01L23/49562 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/3226 ,  H01L2224/48225 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2224/85399

Abstract: A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.

公开(公告)号：US20140117531A1

公开(公告)日：2014-05-01

申请号：US13664418

申请日：2012-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Joachim MAHLER ,  Edward FUERGUT ,  Khalil HOSSEINI ,  Georg MEYER-BERG

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L23/291 ,  H01L21/561 ,  H01L21/568 ,  H01L23/296 ,  H01L23/562 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Described are techniques related to semiconductor devices that make use of encapsulant. In one implementation, a semiconductor device may be manufactured to include at least an encapsulant that includes at least glass particles.

Abstract translation: 描述了与使用密封剂的半导体器件有关的技术。 在一个实施方案中，可以制造半导体器件以至少包括至少包括玻璃颗粒的密封剂。

公开(公告)号：US20170271229A1

公开(公告)日：2017-09-21

申请号：US15462858

申请日：2017-03-19

Applicant: Infineon Technologies AG

Inventor： Norbert Joson SANTOS ,  Edward FUERGUT ,  Sanjay Kumar MURUGAN

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/02 ,  H01L23/495 ,  H01L21/67 ,  H01L33/48 ,  H01L33/54 ,  H01L33/62 ,  H01L33/64 ,  H01L33/60 ,  H01L33/58 ,  H01L23/40 ,  H01L43/02 ,  H01L23/367

CPC classification number: H01L23/3114 ,  H01L21/0206 ,  H01L21/31058 ,  H01L21/565 ,  H01L21/67126 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/4006 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L33/486 ,  H01L33/54 ,  H01L33/58 ,  H01L33/60 ,  H01L33/62 ,  H01L33/642 ,  H01L43/02 ,  H01L2023/405 ,  H01L2023/4081 ,  H01L2023/4087 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2933/005 ,  H01L2933/0066 ,  H01L2933/0075 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: An electronic component which comprises an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating at least part of at least one of the carrier and the electronic chip, and a functional structure covering a surface portion of the encapsulant, wherein at least part of the covered surface portion of the encapsulant is spatially selectively roughened.

公开(公告)号：US20160372399A1

公开(公告)日：2016-12-22

申请号：US15256640

申请日：2016-09-05

Applicant: Infineon Technologies AG

Inventor： Edward FUERGUT ,  Manfred MENGEL

IPC: H01L23/367 ,  H01L21/3105 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

公开(公告)号：US20160365295A1

公开(公告)日：2016-12-15

申请号：US15149207

申请日：2016-05-09

Applicant: Infineon Technologies AG

Inventor： Juergen HOEGERL ,  Edward FUERGUT

IPC: H01L23/31 ,  H01L23/04 ,  H01L23/10 ,  H01L21/56 ,  H01L23/492

CPC classification number: H01L23/31 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/04 ,  H01L23/10 ,  H01L23/142 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/492 ,  H01L23/4924 ,  H01L23/4928 ,  H01L23/49562 ,  H01L23/49877 ,  H01L23/5386 ,  H01L23/544 ,  H01L24/06 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/48 ,  H01L24/50 ,  H01L24/66 ,  H01L24/69 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/86 ,  H01L24/89 ,  H01L24/92 ,  H01L24/97 ,  H01L29/7393 ,  H01L29/868 ,  H01L2223/54486 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29311 ,  H01L2224/29318 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29499 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40137 ,  H01L2224/48137 ,  H01L2224/73201 ,  H01L2224/73213 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73219 ,  H01L2224/73251 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/92142 ,  H01L2224/92144 ,  H01L2224/92147 ,  H01L2224/92148 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/92248 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/1016 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10335 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15162 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/32 ,  H01L2224/69 ,  H01L2224/89 ,  H01L2224/82 ,  H01L2224/86 ,  H01L2224/45099

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power semiconductor devices arranged on the surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices may be electrically coupled to the electrically conductive plate, a plurality of electrically conductive blocks, wherein each electrically conductive block may be electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the surface of the electrically conductive plate may be free from the encapsulation material.

Abstract translation: 提供了半导体布置。 半导体布置可以包括具有表面的导电板，布置在导电板的表面上的多个功率半导体器件，其中多个功率半导体器件中的每个功率半导体器件的第一受控端可以电耦合 导电板，多个导电块，其中每个导电块可以与多个功率半导体器件中的每个功率半导体器件的相应的第二受控端电耦合; 以及封装所述多个功率半导体器件的封装材料，其中所述导电板的表面的至少一个边缘区域可以不含所述封装材料。