公开(公告)号：US09773751B1

公开(公告)日：2017-09-26

申请号：US15214935

申请日：2016-07-20

Applicant: International Business Machines Corporation

Inventor： John U. Knickerbocker ,  Shriya Kumar ,  Jae-Woong Nah

IPC: H01L23/00 ,  H01L23/498

CPC classification number: A61B5/68 ,  A61B2562/12 ,  A61M5/00 ,  A61M2207/00 ,  B23K3/0638 ,  B23K2101/36 ,  H01L21/486 ,  H01L21/76816 ,  H01L21/76852 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/64 ,  H01L24/69 ,  H01L24/83 ,  H01L24/89 ,  H01L2223/6677 ,  H01L2224/27312 ,  H01L2224/32111 ,  H01L2224/32235 ,  H01L2224/325 ,  H01L2224/64 ,  H01L2224/69 ,  H01L2224/83801 ,  H01L2224/89 ,  H01L2224/96 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15332 ,  H05K1/0306 ,  H05K3/4038 ,  H05K2201/0305

Abstract: A method includes forming one or more vias in a first layer, forming one or more vias in at least a second layer different than the first layer, aligning at least a first via in the first layer with at least a second via in the second layer, and bonding the first layer to the second layer by filling the first via and the second via with solder material using injection molded soldering.

公开(公告)号：US20180344245A1

公开(公告)日：2018-12-06

申请号：US16054366

申请日：2018-08-03

Applicant: International Business Machines Corporation

Inventor： John U. Knickerbocker ,  Shriya Kumar ,  Jae-Woong Nah

IPC: A61B5/00 ,  H05K3/40 ,  A61M5/00 ,  B23K3/06 ,  H01L21/48 ,  H01L21/768 ,  H01L23/15 ,  H01L23/498 ,  H01L23/532 ,  H05K1/03 ,  H01L23/00 ,  H01L23/66 ,  H01L23/538 ,  B23K101/36

CPC classification number: A61B5/68 ,  A61B2562/12 ,  A61M5/00 ,  A61M2207/00 ,  B23K3/0638 ,  B23K2101/36 ,  H01L21/486 ,  H01L21/76816 ,  H01L21/76852 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/64 ,  H01L24/69 ,  H01L24/83 ,  H01L24/89 ,  H01L2223/6677 ,  H01L2224/27312 ,  H01L2224/32111 ,  H01L2224/32235 ,  H01L2224/325 ,  H01L2224/64 ,  H01L2224/69 ,  H01L2224/83801 ,  H01L2224/89 ,  H01L2224/96 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15332 ,  H05K1/0306 ,  H05K3/4038 ,  H05K2201/0305

Abstract: An apparatus includes a substrate having one or more vias formed therein. At least one of the vias has at least one liner disposed on at least one sidewall thereof. The apparatus also includes at least one interconnect formed through the at least one via. The one or more interconnects comprise a solder material filled using injection molded soldering.

公开(公告)号：US20160365295A1

公开(公告)日：2016-12-15

申请号：US15149207

申请日：2016-05-09

Applicant: Infineon Technologies AG

Inventor： Juergen HOEGERL ,  Edward FUERGUT

IPC: H01L23/31 ,  H01L23/04 ,  H01L23/10 ,  H01L21/56 ,  H01L23/492

CPC classification number: H01L23/31 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/04 ,  H01L23/10 ,  H01L23/142 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/492 ,  H01L23/4924 ,  H01L23/4928 ,  H01L23/49562 ,  H01L23/49877 ,  H01L23/5386 ,  H01L23/544 ,  H01L24/06 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/48 ,  H01L24/50 ,  H01L24/66 ,  H01L24/69 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/86 ,  H01L24/89 ,  H01L24/92 ,  H01L24/97 ,  H01L29/7393 ,  H01L29/868 ,  H01L2223/54486 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29311 ,  H01L2224/29318 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29499 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40137 ,  H01L2224/48137 ,  H01L2224/73201 ,  H01L2224/73213 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73219 ,  H01L2224/73251 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2224/92142 ,  H01L2224/92144 ,  H01L2224/92147 ,  H01L2224/92148 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/92248 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/1016 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10335 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15162 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/32 ,  H01L2224/69 ,  H01L2224/89 ,  H01L2224/82 ,  H01L2224/86 ,  H01L2224/45099

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power semiconductor devices arranged on the surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices may be electrically coupled to the electrically conductive plate, a plurality of electrically conductive blocks, wherein each electrically conductive block may be electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the surface of the electrically conductive plate may be free from the encapsulation material.

Abstract translation: 提供了半导体布置。 半导体布置可以包括具有表面的导电板，布置在导电板的表面上的多个功率半导体器件，其中多个功率半导体器件中的每个功率半导体器件的第一受控端可以电耦合 导电板，多个导电块，其中每个导电块可以与多个功率半导体器件中的每个功率半导体器件的相应的第二受控端电耦合; 以及封装所述多个功率半导体器件的封装材料，其中所述导电板的表面的至少一个边缘区域可以不含所述封装材料。

公开(公告)号：US20160099393A1

公开(公告)日：2016-04-07

申请号：US14507862

申请日：2014-10-07

Applicant: Epistar Corporation ,  IMEC Taiwan Co.

Inventor： Guan Ru He ,  Jui-Hung Yeh ,  Kevin T. Y. Huang ,  Chih Chung Chen

IPC: H01L33/62 ,  H01L33/36 ,  H01L25/075 ,  H01L33/48

CPC classification number: H01L33/62 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/29 ,  H01L24/40 ,  H01L24/48 ,  H01L24/64 ,  H01L24/66 ,  H01L24/69 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0753 ,  H01L27/153 ,  H01L33/36 ,  H01L33/486 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/29194 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/64 ,  H01L2224/73251 ,  H01L2224/80006 ,  H01L2224/8085 ,  H01L2224/80862 ,  H01L2224/80874 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/89 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2933/0016 ,  H01L2933/0066 ,  H01L2221/68304 ,  H01L2224/45099 ,  H01L2224/32 ,  H01L2224/69 ,  H01L2224/83 ,  H01L2224/08 ,  H01L2224/80 ,  H01L2224/85 ,  H01L2224/84 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: LED chip packaging assembly that facilitates an integrated method for mounting LED chips as a group to be pre-wired to be electrically connected to each other through a pattern of extendable metal wiring lines is provided. LED chips which are electrically connected to each other through extendable metal wiring lines, replace pick and place mounting and the wire bonding processes of the LED chips, respectively. Wafer level MEMS technology is utilized to form parallel wiring lines suspended and connected to various contact pads. Bonding wires connecting the LED chips are made into horizontally arranged extendable metal wiring lines which can be in a spring shape, and allowing for expanding and contracting of the distance between the connected LED chips. A tape is further provided to be bonded to the LED chips, and extended in size to enlarge distance between the LED chips to exceed the one or more prearranged distances.

Abstract translation: 提供了一种便于集成的LED芯片封装组件，用于通过可延伸金属布线的图案将预先布线的LED芯片安装成彼此电连接。 通过可延伸的金属布线电连接的LED芯片分别代替LED芯片的拾取和放置安装以及引线接合工艺。 晶圆级MEMS技术用于形成并联布线，并联连接到各种接触焊盘。 连接LED芯片的接合线被制成水平布置的可延伸的金属布线，其可以是弹簧形状，并且允许连接的LED芯片之间的距离的扩展和收缩。 进一步提供胶带以将其粘合到LED芯片，并且尺寸延伸以扩大LED芯片之间的距离，以超过一个或多个预定距离。

公开(公告)号：US20180005932A1

公开(公告)日：2018-01-04

申请号：US15610885

申请日：2017-06-01

Applicant: International Business Machines Corporation

Inventor： John U. Knickerbocker ,  Shriya Kumar ,  Jae-Woong Nah

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/03

CPC classification number: A61B5/68 ,  A61B2562/12 ,  A61M5/00 ,  A61M2207/00 ,  B23K3/0638 ,  B23K2101/36 ,  H01L21/486 ,  H01L21/76816 ,  H01L21/76852 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/64 ,  H01L24/69 ,  H01L24/83 ,  H01L24/89 ,  H01L2223/6677 ,  H01L2224/27312 ,  H01L2224/32111 ,  H01L2224/32235 ,  H01L2224/325 ,  H01L2224/64 ,  H01L2224/69 ,  H01L2224/83801 ,  H01L2224/89 ,  H01L2224/96 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15332 ,  H05K1/0306 ,  H05K3/4038 ,  H05K2201/0305

Abstract: A method includes forming one or more vias in a substrate, forming a first photoresist layer on a top surface of the substrate and a second photoresist layer on a bottom surface of the substrate, patterning the first photoresist layer and the second photoresist layer to remove at least a first portion of the first photoresist layer and at least a second portion of the second photoresist layer, filling the one or more vias, the first portion and the second portion with solder material using injection molded soldering, and removing remaining portions of the first photoresist layer and the second photoresist layer.

公开(公告)号：US20180005879A1

公开(公告)日：2018-01-04

申请号：US15196558

申请日：2016-06-29

Applicant: International Business Machines Corporation

Inventor： John U. Knickerbocker ,  Shriya Kumar ,  Jae-Woong Nah

IPC: H01L21/768 ,  H01L23/498 ,  H01L23/15 ,  H01L23/532

CPC classification number: A61B5/68 ,  A61B2562/12 ,  A61M5/00 ,  A61M2207/00 ,  B23K3/0638 ,  B23K2101/36 ,  H01L21/486 ,  H01L21/76816 ,  H01L21/76852 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/64 ,  H01L24/69 ,  H01L24/83 ,  H01L24/89 ,  H01L2223/6677 ,  H01L2224/27312 ,  H01L2224/32111 ,  H01L2224/32235 ,  H01L2224/325 ,  H01L2224/64 ,  H01L2224/69 ,  H01L2224/83801 ,  H01L2224/89 ,  H01L2224/96 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15332 ,  H05K1/0306 ,  H05K3/4038 ,  H05K2201/0305

Abstract: A method includes forming one or more vias in a substrate, forming at least one liner on at least one sidewall of at least one of the vias, and filling said at least one via with solder material using injection molded soldering. The at least one liner may comprise a solder adhesion layer, a barrier layer, or a combination of a barrier layer and a solder adhesion layer.

公开(公告)号：US09761516B1

公开(公告)日：2017-09-12

申请号：US15214914

申请日：2016-07-20

Applicant: International Business Machines Corporation

Inventor： John U. Knickerbocker ,  Shriya Kumar ,  Jae-Woong Nah

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/03

CPC classification number: A61B5/68 ,  A61B2562/12 ,  A61M5/00 ,  A61M2207/00 ,  B23K3/0638 ,  B23K2101/36 ,  H01L21/486 ,  H01L21/76816 ,  H01L21/76852 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/64 ,  H01L24/69 ,  H01L24/83 ,  H01L24/89 ,  H01L2223/6677 ,  H01L2224/27312 ,  H01L2224/32111 ,  H01L2224/32235 ,  H01L2224/325 ,  H01L2224/64 ,  H01L2224/69 ,  H01L2224/83801 ,  H01L2224/89 ,  H01L2224/96 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15332 ,  H05K1/0306 ,  H05K3/4038 ,  H05K2201/0305

Abstract: A method includes forming one or more vias in a substrate, forming a first photoresist layer on a top surface of the substrate and a second photoresist layer on a bottom surface of the substrate, patterning the first photoresist layer and the second photoresist layer to remove at least a first portion of the first photoresist layer and at least a second portion of the second photoresist layer, filling the one or more vias, the first portion and the second portion with solder material using injection molded soldering, and removing remaining portions of the first photoresist layer and the second photoresist layer.

公开(公告)号：US20020145188A1

公开(公告)日：2002-10-10

申请号：US10161674

申请日：2002-06-05

Inventor： Hironori Kodama ,  Masahiro Nagasu ,  Hirokazu Inoue ,  Yasuo Osone ,  Shigeta Ueda ,  Kazuji Yamada

IPC: H01L023/02

CPC classification number: H01L24/72 ,  H01L23/051 ,  H01L24/05 ,  H01L24/89 ,  H01L25/072 ,  H01L25/117 ,  H01L2224/05551 ,  H01L2224/06181 ,  H01L2224/45124 ,  H01L2224/89 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48

Abstract: Control electrode wirings which are led out from control electrodes over a number of chips built in a flat package and insulating members which are provided in order to insulate the control electrode wirings from main electrode wirings are also given function of positioning of the respective semiconductor chips in the flat package. Further, a one-piece control electrode wiring net is housed in the common electrodes of the package and the electrodes which are led out from the control electrodes of the respective semiconductor chips are connected to the net to simplify the processing of a large number of gate signal wirings.

公开(公告)号：US20230377938A1

公开(公告)日：2023-11-23

申请号：US18265902

申请日：2021-02-26

Applicant: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wanli GUO ,  Tianjian LIU

IPC: H01L21/683 ,  H01L21/60 ,  H01L21/768 ,  H01L21/784 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L21/6836 ,  H01L21/60 ,  H01L21/76804 ,  H01L21/784 ,  H01L24/89 ,  H01L21/02076 ,  H01L2224/89 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68372 ,  H01L2924/37001

Abstract: A die bonding method is disclosed, through coating bonding adhesive on front side of device wafer and bonding carrier wafer thereto, back-side connection structure can be formed on back side of device wafer to lead out an interconnect structure in device wafer to back side of device wafer, and dies thereon can be bonded at front sides to target wafer. Moreover, after device wafer is debonded from carrier wafer, the bonding adhesive is retained on front side of device wafer to provide protection to front side of device wafer during subsequent dicing of device wafer, and to avoid particles or etching by-products produced during dicing process from adhering to front side of device wafer. Such etching by-products are subsequently removed along with the bonding adhesive, ensuring cleanness of front sides of individual dies resulting from dicing process and improved quality of bonding of dies at front sides to target wafer.

公开(公告)号：US20180301609A1

公开(公告)日：2018-10-18

申请号：US16006857

申请日：2018-06-13

Applicant: Epistar Corporation ,  IMEC Taiwan Co.

Inventor： Guan Ru He ,  Jui-Hung Yeh ,  Kevin T. Y. Huang ,  Chih Chung Chen

IPC: H01L33/62 ,  H01L21/683 ,  H01L25/075 ,  H01L23/00 ,  H01L33/48 ,  H01L33/36 ,  H01L27/15

CPC classification number: H01L33/62 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/29 ,  H01L24/40 ,  H01L24/48 ,  H01L24/64 ,  H01L24/66 ,  H01L24/69 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0753 ,  H01L27/153 ,  H01L33/36 ,  H01L33/486 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/29194 ,  H01L2224/32 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/64 ,  H01L2224/73251 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/8085 ,  H01L2224/80862 ,  H01L2224/80874 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/89 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2933/0016 ,  H01L2933/0066 ,  H01L2224/45099 ,  H01L2224/69 ,  H01L2224/83 ,  H01L2224/08 ,  H01L2224/85 ,  H01L2224/84 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: LED chip packaging assembly that facilitates an integrated method for mounting LED chips as a group to be pre-wired to be electrically connected to each other through a pattern of extendable metal wiring lines is provided. LED chips which are electrically connected to each other through extendable metal wiring lines, replace pick and place mounting and the wire bonding processes of the LED chips, respectively. Wafer level MEMS technology is utilized to form parallel wiring lines suspended and connected to various contact pads. Bonding wires connecting the LED chips are made into horizontally arranged extendable metal wiring lines which can be in a spring shape, and allowing for expanding and contracting of the distance between the connected LED chips. A tape is further provided to be bonded to the LED chips, and extended in size to enlarge distance between the LED chips to exceed the one or more prearranged distances.