公开(公告)号：US08482116B2

公开(公告)日：2013-07-09

申请号：US13130169

申请日：2009-11-10

申请人： Romain Coffy ,  Remi Brechignac ,  Carlo Cognetti de Martiis

发明人： Romain Coffy ,  Remi Brechignac ,  Carlo Cognetti de Martiis

IPC分类号： H01L23/04

CPC分类号： H01L25/50 ,  H01L21/565 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/0401

摘要： A semiconductor device includes at least one first component (5) (for example, a first integrated circuit), having a front face provided with electrical connection pads. The first component is embedded in a support layer (2) is a position such that the front face of the first component is not covered and lies parallel to a first face of the support layer. An intermediate layer (8) is formed on the front face of the first component and on the first face of the support layer. An electrical connection network (9) within the intermediate layer selectively connects to the electrical connection pads of the first component. The device further includes at least one second component (11) (for example, a second integrate circuit, having one face placed above the intermediate layer and provided with electrical connection pads selectively connected to the electrical connection network. Electrical connection vias (17) pass through the support layer and selectively connect the electrical connection network to an external electrical connection formed on a second face of the support layer.

摘要翻译： 半导体器件包括至少一个第一部件（5）（例如，第一集成电路），其具有设置有电连接焊盘的正面。 第一部件嵌入在支撑层（2）中，是使得第一部件的前表面不被覆盖并平行于支撑层的第一面的位置。 在第一部件的正面和支撑层的第一面上形成中间层（8）。 中间层内的电连接网络（9）选择性地连接到第一部件的电连接焊盘。 该装置还包括至少一个第二部件（11）（例如，第二集成电路，其中一个面放置在中间层的上方，并且具有选择性地连接到电连接网络的电连接焊盘）。电连接通孔（17）通过 通过支撑层并且将电连接网络选择性地连接到形成在支撑层的第二面上的外部电连接。

公开(公告)号：US20110248397A1

公开(公告)日：2011-10-13

申请号：US13130169

申请日：2009-11-10

申请人： Romain Coffy ,  Remi Brechignac ,  Carlo Cognetti De Martiis

发明人： Romain Coffy ,  Remi Brechignac ,  Carlo Cognetti De Martiis

IPC分类号： H01L25/065 ,  H01L21/98 ,  H01L23/538

CPC分类号： H01L25/50 ,  H01L21/565 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/0401

摘要： A semiconductor device includes at least one first component (5) (for example, a first integrated circuit), having a front face provided with electrical connection pads. The first component is embedded in a support layer (2) is a position such that the front face of the first component is not covered and lies parallel to a first face of the support layer. An intermediate layer (8) is formed on the front face of the first component and on the first face of the support layer. An electrical connection network (9) within the intermediate layer selectively connects to the electrical connection pads of the first component. The device further includes at least one second component (11) (for example, a second integrate circuit, having one face placed above the intermediate layer and provided with electrical connection pads selectively connected to the electrical connection network. Electrical connection vias (17) pass through the support layer and selectively connect the electrical connection network to an external electrical connection formed on a second face of the support layer.

摘要翻译： 半导体器件包括至少一个第一部件（5）（例如，第一集成电路），其具有设置有电连接焊盘的正面。 第一部件嵌入在支撑层（2）中，是使得第一部件的前表面不被覆盖并平行于支撑层的第一面的位置。 在第一部件的正面和支撑层的第一面上形成中间层（8）。 中间层内的电连接网络（9）选择性地连接到第一部件的电连接焊盘。 该装置还包括至少一个第二部件（11）（例如，第二集成电路，其中一个面放置在中间层的上方，并且具有选择性地连接到电连接网络的电连接焊盘）。电连接通孔（17）通过 通过支撑层并且将电连接网络选择性地连接到形成在支撑层的第二面上的外部电连接。

公开(公告)号：US09136292B2

公开(公告)日：2015-09-15

申请号：US13541066

申请日：2012-07-03

申请人： Romain Coffy ,  Remi Brechignac

发明人： Romain Coffy ,  Remi Brechignac

IPC分类号： H01L27/00 ,  H01L27/146 ,  G01S7/481 ,  G01S17/02 ,  H01L25/16 ,  H01L31/167 ,  H01L31/173 ,  H01L33/48 ,  H01L33/54

CPC分类号： H01L27/14618 ,  G01S7/4813 ,  G01S17/026 ,  H01L25/167 ,  H01L27/14603 ,  H01L27/14643 ,  H01L27/14647 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/167 ,  H01L31/173 ,  H01L33/486 ,  H01L33/54 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An electronic package includes a substrate wafer having front and rear faces. An emitting integrated circuit chip is mounted to the front face of the substrate wafer and includes a light radiation optical emitter. A receiving integrated circuit chip is also mounted to the front face of the substrate wafer and includes at least one light radiation optical sensor. A transparent encapsulant extends above the optical sensor and the optical emitter. An opaque encapsulant encapsulates the transparent encapsulant. The opaque encapsulant has a front window situated above the optical emitter and which is offset laterally relative to the optical sensor. The transparent encapsulant accordingly has an uncovered front face situated above the optical emitter and offset laterally relative to the optical sensor. The opaque encapsulant may include an additional front window. The receiving integrated circuit chip further includes a second optical sensor situated opposite the additional front window.

摘要翻译： 电子封装包括具有正面和背面的衬底晶片。 发光集成电路芯片安装在基板晶片的正面，并包括光辐射光发射器。 接收集成电路芯片也安装在基板晶片的正面，并且包括至少一个光辐射光学传感器。 透明密封剂在光学传感器和光发射器之上延伸。 不透明的密封剂封装透明密封剂。 不透明密封剂具有位于光发射器上方并且相对于光学传感器横向偏移的前窗。 因此，透明密封剂具有位于光发射器上方并且相对于光学传感器横向偏移的未覆盖的正面。 不透明的密封剂可以包括另外的前窗。 接收集成电路芯片还包括与附加前窗相对的第二光学传感器。

公开(公告)号：US20130012276A1

公开(公告)日：2013-01-10

申请号：US13541066

申请日：2012-07-03

申请人： Romain Coffy ,  Remi Brechignac

发明人： Romain Coffy ,  Remi Brechignac

IPC分类号： H01L33/48 ,  H04W88/02

CPC分类号： H01L27/14618 ,  G01S7/4813 ,  G01S17/026 ,  H01L25/167 ,  H01L27/14603 ,  H01L27/14643 ,  H01L27/14647 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/167 ,  H01L31/173 ,  H01L33/486 ,  H01L33/54 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An electronic package includes a substrate wafer having front and rear faces. An emitting integrated circuit chip is mounted to the front face of the substrate wafer and includes a light radiation optical emitter. A receiving integrated circuit chip is also mounted to the front face of the substrate wafer and includes at least one light radiation optical sensor. A transparent encapsulant extends above the optical sensor and the optical emitter. An opaque encapsulant encapsulates the transparent encapsulant. The opaque encapsulant has a front window situated above the optical emitter and which is offset laterally relative to the optical sensor. The transparent encapsulant accordingly has an uncovered front face situated above the optical emitter and offset laterally relative to the optical sensor. The opaque encapsulant may include an additional front window. The receiving integrated circuit chip further includes a second optical sensor situated opposite the additional front window.

摘要翻译： 电子封装包括具有正面和背面的衬底晶片。 发光集成电路芯片安装在基板晶片的正面，并包括光辐射光发射器。 接收集成电路芯片也安装在基板晶片的正面，并且包括至少一个光辐射光学传感器。 透明密封剂在光学传感器和光发射器之上延伸。 不透明的密封剂封装透明密封剂。 不透明密封剂具有位于光发射器上方并且相对于光学传感器横向偏移的前窗。 因此，透明密封剂具有位于光发射器上方并且相对于光学传感器横向偏移的未覆盖的正面。 不透明的密封剂可以包括另外的前窗。 接收集成电路芯片还包括与附加前窗相对的第二光学传感器。

公开(公告)号：US08786084B2

公开(公告)日：2014-07-22

申请号：US12751088

申请日：2010-03-31

申请人： Romain Coffy ,  Jean-François Sauty

发明人： Romain Coffy ,  Jean-François Sauty

IPC分类号： H01L23/488 ,  H01L23/00 ,  H01L21/60

CPC分类号： H01L24/85 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/274 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/85375 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01202 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/20752 ,  Y10T29/49126 ,  H01L2224/85 ,  H01L2924/01204 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.

摘要翻译： 半导体封装包括附接到具有导电路径的支撑件的半导体管芯，所述半导体管芯具有通过第一金属组合物的接合线电连接到支撑体上的导电路径上的接合焊盘，所述接合线 并且所述接合垫涂覆有第二金属组合物的保护层。

公开(公告)号：US20130009173A1

公开(公告)日：2013-01-10

申请号：US13531638

申请日：2012-06-25

申请人： Julien Vittu ,  Romain Coffy

发明人： Julien Vittu ,  Romain Coffy

IPC分类号： H01L33/48

CPC分类号： G01S17/026 ,  G01J1/0271 ,  G01J1/0403 ,  G01J1/0407 ,  G01S7/4813 ,  H01L25/167 ,  H01L31/16 ,  H01L33/48 ,  H01L2224/48227 ,  H01L2224/48091 ,  H01L2924/00014

摘要： An electronic package includes a substrate wafer having front and rear faces and a through passage having a front window and a blind cavity communicating laterally with the front window. A receiving integrated circuit chip is mounted on the rear face and includes an optical sensor situated opposite the blind cavity. A transparent encapsulant extends above the optical sensor and at least partially fills the through passage. An emitting integrated circuit chip, embedded in the transparent encapsulant, includes an optical emitter of luminous radiation. The emitting integrated circuit chip may be mounted to the front face or within the through passage to the receiving integrated circuit chip. The substrate wafer may further include a second through passage. The receiving integrated circuit chip further includes a second optical sensor situated opposite the second through passage. A cover plate is mounted to the front face at the second through passage.

摘要翻译： 电子封装包括具有前表面和后表面的基底晶片和具有前窗和与前窗横向连通的盲腔的通孔。 接收集成电路芯片安装在后表面上并且包括位于盲腔相对的光学传感器。 透明密封剂在光学传感器上方延伸并且至少部分地填充通过通道。 嵌入在透明密封剂中的发射集成电路芯片包括发光体的发光体。 发射集成电路芯片可以安装到前面或通向接收集成电路芯片的通路内。 衬底晶片还可以包括第二穿通通道。 接收集成电路芯片还包括与第二贯穿通道相对的第二光学传感器。 盖板在第二通道处被安装到前表面。

公开(公告)号：US20110092000A1

公开(公告)日：2011-04-21

申请号：US12990684

申请日：2009-05-20

申请人： Romain Coffy

发明人： Romain Coffy

IPC分类号： H01L21/66

CPC分类号： G01R31/2884 ,  G01R1/0408 ,  G01R31/2822 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/11 ,  H01L2924/00

摘要： A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.

摘要翻译： 一种用于制造和测试集成电路的方法，包括以下步骤：在所述集成电路的上部形成钝化层，所述钝化层包括在所述集成电路的最后一个互连堆叠的金属轨道的水平面处的开口; 在所述开口中形成通过导电轨道部分连接到形成在所述钝化层上的第二焊盘的第一焊盘，所述第一焊盘用于所述集成电路的连接; 通过将测试头与第二个焊盘接触来测试集成电路; 以及消除所述导电轨道部分中的至少一个的至少一部分。

公开(公告)号：US20090134514A1

公开(公告)日：2009-05-28

申请号：US12262982

申请日：2008-10-31

申请人： Romain Coffy ,  Jacky Seiller ,  Gil Provent

发明人： Romain Coffy ,  Jacky Seiller ,  Gil Provent

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H05K3/242 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/11422 ,  H01L2224/11472 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H05K3/3473 ,  H05K2203/043 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A method for fabricating electrical bonding pads on one face of a wafer includes the production of electrically conductive areas and electrical connection branches connecting these conductive areas. A layer of mask material is deposited and openings are produced in this mask layer which extend above said conductive areas and at least some of which extend at least partly beyond the peripheral edges of the underlying conductive areas. Blocks made of a solder material are produces in the openings by electrodeposition in a bath. The mask material is then removed along with the connection branches. The wafer is passed through or placed in an oven so as to shape, on the conductive areas, the blocks into substantially domed electrical bonding pads.

摘要翻译： 用于在晶片的一个面上制造电接合焊盘的方法包括制造导电区域和连接这些导电区域的电连接分支。 沉积掩模材料层，并且在该掩模层中产生开口，该掩模层在所述导电区域之上延伸，并且至少其中一些延伸至少部分地超过下面的导电区域的周边边缘。 通过在浴中电沉积在开口中产生由焊料材料制成的块。 然后将掩模材料与连接分支一起移除。 将晶片通过或放置在烘箱中，以在导电区域上将块形成为基本上圆顶的电接合焊盘。

公开(公告)号：US20060273813A1

公开(公告)日：2006-12-07

申请号：US11407855

申请日：2006-04-20

申请人： Romain Coffy

发明人： Romain Coffy

IPC分类号： G01R31/02

CPC分类号： H01L23/552 ,  H01L23/055 ,  H01L23/06 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16152 ,  H05K1/0218 ,  H05K3/284 ,  H05K9/0022 ,  H05K2203/041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45015 ,  H01L2924/207

摘要： A device for protecting an electronic circuit comprising a support to which are attached at least two circuit portions, each comprising at least one integrated circuit chip. The device comprises a wafer of a semiconductor material covered with a conductive layer arranged parallel to the support, the wafer being connected to the support by conductive pillars distributed around each circuit portion and in contact with the conductive layer.

摘要翻译： 一种用于保护电子电路的装置，包括支撑件，至少两个电路部分连接至所述支架，每个电路部分包括至少一个集成电路芯片。 该器件包括半导体材料的晶片，该半导体材料被平行于支撑体布置的导电层覆盖，晶片通过分布在每个电路部分周围并与导电层接触的导电柱连接到支撑体。

公开(公告)号：US08928148B2

公开(公告)日：2015-01-06

申请号：US13229924

申请日：2011-09-12

申请人： Romain Coffy ,  Yann Guillou

发明人： Romain Coffy ,  Yann Guillou

IPC分类号： H01L29/72 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/36 ,  H01L23/498 ,  H01L23/00 ,  H01L23/42 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/14519 ,  H01L2224/17519 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A first component includes a slice formed from an integrated circuit chip having a front face and a rear face. An encapsulation block encapsulates the integrated circuit chip such that front and rear faces of the chip and front and rear faces of the encapsulation block are co-planar to form front and rear faces of the slice. Front and rear electrical connection networks are provided on the front and rear faces, respectively, with the electrical connection networks linked by electrical connection vias passing through the encapsulation block. A thermal transfer layer at least partially covers the rear face. A second component may be behind and at a distance from the first component. Connection elements interposed between the first component and the second component include both thermal connection elements in contact with the thermal transfer layer and electrical connection elements interconnecting the first and second components.

摘要翻译： 第一部件包括由具有前表面和后表面的集成电路芯片形成的切片。 封装块封装集成电路芯片，使得芯片的前表面和后表面以及封装块的前后表面是共面的，以形成切片的前后面。 前后电气连接网络分别设置在前表面和后表面上，电连接网络通过通过封装块的电连接通孔连接。 至少部分地覆盖后表面的热转印层。 第二组件可以在第一组件的后面并且距离第一组件一定距离。 插入在第一部件和第二部件之间的连接元件包括与热传递层接触的热连接元件和互连第一和第二部件的电连接元件。