公开(公告)号：US07217645B2

公开(公告)日：2007-05-15

申请号：US10372392

申请日：2003-02-25

申请人： Shiro Yamashita ,  Masahide Harada ,  Kenichi Yamamoto ,  Munehiro Yamada ,  Ryosuke Kimoto

发明人： Shiro Yamashita ,  Masahide Harada ,  Kenichi Yamamoto ,  Munehiro Yamada ,  Ryosuke Kimoto

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3436 ,  H05K3/3463 ,  H01L2224/29099 ,  H01L2924/00014 ,  H01L2924/00

摘要： Solder is connected to the electrodes of the circuit board by using a temperature profile with a constant fusion temperature, a connection interface strength evaluation test is carried out on the soldered joints to obtain an appropriate reflow range free of decreases in the strength at the connection interface. On the basis of the appropriate reflow range obtained and using as the basis the chemical compound thickness which is determined uniquely by heat load, an appropriate reflow range in an optional temperature profile with one temperature peak is obtained. By carrying out connection in this appropriate reflow range, soldered joints can be obtained without decreases in the connection interface strength in the large-scale production stage.

摘要翻译： 通过使用恒定熔融温度的温度分布将焊料连接到电路板的电极，在焊接接头上进行连接界面强度评估测试，以获得在连接界面处强度没有降低的适当回流范围 。 基于获得的适当的回流范围和以热负荷唯一确定的化合物厚度为基准，获得具有一个温度峰值的任选温度曲线中的适当回流范围。 通过在适当的回流范围内实现连接，可以在大规模生产阶段的连接界面强度不降低的情况下获得焊接接头。

公开(公告)号：US06879041B2

公开(公告)日：2005-04-12

申请号：US10396326

申请日：2003-03-26

申请人： Kenichi Yamamoto ,  Toshiaki Morita ,  Munehiro Yamada ,  Ryosuke Kimoto

发明人： Kenichi Yamamoto ,  Toshiaki Morita ,  Munehiro Yamada ,  Ryosuke Kimoto

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H05K3/24 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/013 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/244 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05541 ,  H01L2224/05005

摘要： The impact strength resistance of a solder joint portion of a semiconductor device is improved. The semiconductor device has a joint structure wherein a jointing layer which does not contain sulfur substantially is arranged between an underlying conductive layer and a lead-free solder layer and further between the jointing layer and the lead-free solder layer is formed an alloy layer comprising elements of these layers.

摘要翻译： 半导体器件的焊接部的耐冲击强度提高。 半导体器件具有接合结构，其中基本上不含硫的接合层布置在下面的导电层和无铅焊料层之间，并且在接合层和无铅焊料层之间形成合金层，其包括 这些层的元素。

公开(公告)号：US07211892B2

公开(公告)日：2007-05-01

申请号：US11146044

申请日：2005-06-07

申请人： Shiro Yamashita ,  Yoichi Abe ,  Kenichi Yamamoto ,  Ryosuke Kimoto ,  Hiroshi Kawakubo

发明人： Shiro Yamashita ,  Yoichi Abe ,  Kenichi Yamamoto ,  Ryosuke Kimoto ,  Hiroshi Kawakubo

IPC分类号： H01L29/40

CPC分类号： H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/067 ,  H05K3/244 ,  H05K3/3463 ,  H05K2201/0305 ,  H05K2203/0361 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 μm or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3×10−3 (Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.

摘要翻译： 为了抑制由于在具有电极焊盘的半导体器件中电极焊盘的连接界面强度的劣化及其翘曲导致的连接故障，形成在电极焊盘上的金属层和形成在金属上的金属凸块 在本发明中，在金属层中含有金（Au），金属凸块由主要由Sn制成的焊料制成，并且设计成在电极焊盘中的每单位面积的平均高度H为100mum以下， 并且溶解在焊料中的金属层的Au浓度设定为1.3×10 -3（Vol％）以下。 更优选地，金属凸块包含钯（Pd），并且通过组合使用浸渍和糊印来进行用于在电极焊盘上形成金属凸块的焊料涂层。

公开(公告)号：US20060151877A1

公开(公告)日：2006-07-13

申请号：US11146044

申请日：2005-06-07

申请人： Shiro Yamashita ,  Yoichi Abe ,  Kenichi Yamamoto ,  Ryosuke Kimoto ,  Hiroshi Kawakubo

发明人： Shiro Yamashita ,  Yoichi Abe ,  Kenichi Yamamoto ,  Ryosuke Kimoto ,  Hiroshi Kawakubo

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/067 ,  H05K3/244 ,  H05K3/3463 ,  H05K2201/0305 ,  H05K2203/0361 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 μm or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3×10−3 (Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.

摘要翻译： 为了抑制由于在具有电极焊盘的半导体器件中电极焊盘的连接界面强度的劣化及其翘曲导致的连接故障，形成在电极焊盘上的金属层和形成在金属上的金属凸块 在本发明中，在金属层中含有金（Au），金属凸块由主要由Sn制成的焊料制成，并且设计成在电极焊盘中的每单位面积的平均高度H为100mum以下， 并且溶解在焊料中的金属层的Au浓度设定为1.3×10 -3（Vol％）以下。 更优选地，金属凸块包含钯（Pd），并且通过组合使用浸渍和糊印来进行用于在电极焊盘上形成金属凸块的焊料涂层。

公开(公告)号：US20130067424A1

公开(公告)日：2013-03-14

申请号：US13593499

申请日：2012-08-23

申请人： Kenichi YAMAMOTO ,  Ryosuke Kimoto ,  Kenya Kawano ,  Hisashi Tanie ,  Yasuhiro Naka

发明人： Kenichi YAMAMOTO ,  Ryosuke Kimoto ,  Kenya Kawano ,  Hisashi Tanie ,  Yasuhiro Naka

IPC分类号： G06F19/00 ,  G06F17/50

CPC分类号： G06F17/5018 ,  G06F2217/40 ,  G06F2217/76 ,  G06F2217/80

摘要： A life prediction method of an electronic device in which the life prediction accuracy is more improved than that in a related art technique, and a design method of an electronic device based on the above method, are established. Life prediction is performed by incorporating either of a change in a physical property of a solder joint portion and a change in the fatigue life of a solder, the changes occurring when left at a high temperature. The change in a physical property of the solder joint portion or the change in the fatigue life of the solder is determined from the relationship between a heat treatment temperature and a heat treatment time. These changes are then formulated to be incorporated into the life prediction.

摘要翻译： 建立了寿命预测精度比现有技术更好的电子设备的寿命预测方法，并且建立了基于上述方法的电子设备的设计方法。 寿命预测通过掺入焊接部分的物理性质的改变和焊料的疲劳寿命的变化来执行，当在高温下放置时发生的变化。 根据热处理温度和热处理时间的关系，确定焊点的物性的变化或焊料的疲劳寿命的变化。 然后将这些变化制定为纳入人生预测。

公开(公告)号：US07091620B2

公开(公告)日：2006-08-15

申请号：US11116209

申请日：2005-04-28

申请人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

发明人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

公开(公告)号：US20050040509A1

公开(公告)日：2005-02-24

申请号：US10860073

申请日：2004-06-04

申请人： Takashi Kikuchi ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Takashi Miwa ,  Chikako Imura ,  Takafumi Nishita ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Masaru Kawakami

发明人： Takashi Kikuchi ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Takashi Miwa ,  Chikako Imura ,  Takafumi Nishita ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Masaru Kawakami

IPC分类号： H01L23/12 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10 ,  H05K1/00 ,  H01L21/48 ,  H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L24/28 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.

摘要翻译： 对于半导体器件的高密度封装，半导体器件具有多层衬底，与多层衬底电连接的第一级芯片，在多层衬底上分层堆叠的其它封装衬底，并且每个衬底连接到 通过焊球，第二级，第三级和第四级芯片分别与其他封装衬底电连接的底层布线衬底以及设置在底部多层衬底上的焊球。 具有逻辑芯片的底部多层基板中的布线层数大于具有存储芯片的封装基板中的布线层的数量，由此半导体器件可以具有不用于将焊丝分布到焊球的布线层， 布线层中的布线可用于安装另一半导体元件或无源元件，以实现作为堆叠型封装的半导体器件的高密度封装。

公开(公告)号：US5714405A

公开(公告)日：1998-02-03

申请号：US721240

申请日：1996-09-26

申请人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

发明人： Kunihiro Tsubosaki ,  Michio Tanimoto ,  Kunihiko Nishi ,  Masahiro Ichitani ,  Shunji Koike ,  Kazunari Suzuki ,  Ryosuke Kimoto ,  Ichiro Anjoh ,  Taisei Jin ,  Akihiko Iwaya ,  Gen Murakami ,  Masamichi Ishihara ,  Junichi Arita

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L21/60

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85424 ,  H01L2225/1029 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/49121

摘要： A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

摘要翻译： 一种半导体器件，其具有通过绝缘粘合剂膜固定到半导体芯片的主表面并与半导体芯片的各个外部端子电连接的内部引线。 可以关于芯片尺寸的半导体器件被配置为使得外引线从每个内引线连续地延伸到与半导体芯片的主表面相对的后表面，以便保持引线和外部器件 导通。

公开(公告)号：US07332800B2

公开(公告)日：2008-02-19

申请号：US10860073

申请日：2004-06-04

申请人： Takashi Kikuchi ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Takashi Miwa ,  Chikako Imura ,  Takafumi Nishita ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Masaru Kawakami

发明人： Takashi Kikuchi ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Takashi Miwa ,  Chikako Imura ,  Takafumi Nishita ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Masaru Kawakami

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L24/28 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.

摘要翻译： 对于半导体器件的高密度封装，半导体器件具有多层衬底，与多层衬底电连接的第一级芯片，在多层衬底上分层堆叠的其它封装衬底，并且每个衬底连接到 通过焊球，第二级，第三级和第四级芯片分别与其他封装衬底电连接的底层布线衬底以及设置在底部多层衬底上的焊球。 具有逻辑芯片的底部多层基板中的布线层数大于具有存储芯片的封装基板中的布线层的数量，由此半导体器件可以具有不用于将焊丝分布到焊球的布线层， 布线层中的布线可用于安装另一半导体元件或无源元件，以实现作为堆叠型封装的半导体器件的高密度封装。

公开(公告)号：US20060261494A1

公开(公告)日：2006-11-23

申请号：US11492165

申请日：2006-07-25

申请人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masanori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe

发明人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masanori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe

IPC分类号： H01L23/48

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

摘要翻译： 半导体器件包括形成有连接端子的半导体芯片，插入在芯片的主表面之间的弹性结构和形成有连接到连接端子的布线的布线基板，以及连接到连接端子的另一端的凸起电极 布线。 连接端子可以在芯片主表面的中心部分或周边部分，并且弹性结构和布线基板都不设置在连接端子的位置处。 树脂体至少密封连接端子和暴露的布线的第一端（引线）。 在连接端子位于芯片主表面的周边部分的方案中，布线基板突出超过布置有连接端子的芯片边界，并且树脂体形状被布线基板的突出部分限制 。