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    Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces
    2.
    发明授权
    Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces 有权
    用于成像和切割半导体晶片和其他半导体工件的方法和系统

    公开(公告)号：US09579825B2

    公开(公告)日：2017-02-28

    申请号：US14093682

    申请日：2013-12-02

    Applicant: Micron Technology, Inc.

    Inventor： Warren M. Farnworth ,  Tom A. Muntifering ,  Paul J. Clawson

    IPC: B28D5/00 ,  B23K26/042 ,  B23Q15/22 ,  H01L21/78 ,  B26F3/00 ,  B23K26/40

    CPC classification number: H01L22/20 ,  B23K26/03 ,  B23K26/042 ,  B23K26/044 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/56 ,  B23Q15/22 ,  B26F3/004 ,  B28D5/0064 ,  H01L21/78 ,  Y10T83/141 ,  Y10T83/178 ,  Y10T83/538

    Abstract: Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system for singulating microelectronic devices from a substrate includes an X-ray imaging system having an X-ray source spaced apart from an X-ray detector. The X-ray source can emit a beam of X-rays through the substrate and onto the X-ray detector, and X-ray detector can generate an X-ray image of at least a portion of the substrate. A method in accordance with another embodiment includes detecting spacing information for irregularly spaced dies of a semiconductor workpiece. The method can further include automatically controlling a process for singulating the dies of the semiconductor workpiece, based at least in part on the spacing information. For example, individual dies can be singulated from a workpiece via non-straight line cuts and/or multiple cutter passes.

    Abstract translation: 本文公开了用于成像和切割半导体晶片和其它微电子器件基板的方法和系统。 在一个实施例中，用于从衬底分离微电子器件的系统包括具有与X射线检测器间隔开的X射线源的X射线成像系统。 X射线源可以通过衬底和X射线检测器发射X射线束，并且X射线检测器可以产生至少部分衬底的X射线图像。 根据另一实施例的方法包括检测半导体工件的不规则间隔的管芯的间隔信息​​。 该方法还可以包括至少部分地基于间隔信息来自动控制用于对半导体工件的管芯进行分割的工艺。 例如，可以通过非直线切割和/或多个切割器通过从工件分离各个模具。

    Imager device with electric connections to electrical device
    3.
    发明授权
    Imager device with electric connections to electrical device 有权
    具有与电气设备电连接的成像仪器

    公开(公告)号：US08951858B2

    公开(公告)日：2015-02-10

    申请号：US13861580

    申请日：2013-04-12

    Applicant: Micron Technology, Inc.

    Inventor： Warren M. Farnworth

    IPC: H01L27/146 ,  H01L31/0232

    CPC classification number: H01L31/0232 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

    Abstract: An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer. A method of making an imager device is disclosed including providing a first substrate having a first conductive layer and an array of photosensitive elements formed above the first substrate, forming a conductive member that extends through the first substrate and is conductively coupled to the first conductive layer, forming a standoff structure above the first substrate, forming a patterned conductive layer above the standoff structure, the patterned conductive layer being conductively coupled to the first conductive layer, and conductively coupling an electrically powered device to the patterned conductive layer positioned above the standoff structure.

    Abstract translation: 公开了一种成像器件，其包括具有形成在其上的感光元件阵列的第一衬底，形成在第一衬底上方的第一导电层，延伸穿过第一衬底的第一导电构件，第一导电构件导电耦合到第一衬底 导电层，形成在第一基板上方的间隔结构，形成在支架结构上方的第二导电层，第二导电层导电耦合到第一导电层，以及位于支架结构之上的电动设备，电动设备 电耦合到第二导电层。 公开了一种制造成像器件的方法，包括提供具有第一导电层的第一衬底和形成在第一衬底上方的感光元件阵列的第一衬底，形成延伸穿过第一衬底的导电构件并与第一导电层 ，在所述第一基板上方形成间隔结构，在所述支座结构之上形成图案化导电层，所述图案化导电层导电耦合到所述第一导电层，并且将电动装置导电耦合到所述支架结构上方的图案化导电层 。

    IMAGER DEVICE WITH ELECTRIC CONNECTIONS TO ELECTRICAL DEVICE
    5.
    发明申请
    IMAGER DEVICE WITH ELECTRIC CONNECTIONS TO ELECTRICAL DEVICE 有权
    具有电气连接到电气设备的图像装置

    公开(公告)号：US20130249036A1

    公开(公告)日：2013-09-26

    申请号：US13861580

    申请日：2013-04-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Warren M. Farnworth

    IPC: H01L31/0232

    CPC classification number: H01L31/0232 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

    Abstract: An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer. A method of making an imager device is disclosed including providing a first substrate having a first conductive layer and an array of photosensitive elements formed above the first substrate, forming a conductive member that extends through the first substrate and is conductively coupled to the first conductive layer, forming a standoff structure above the first substrate, forming a patterned conductive layer above the standoff structure, the patterned conductive layer being conductively coupled to the first conductive layer, and conductively coupling an electrically powered device to the patterned conductive layer positioned above the standoff structure.

    Abstract translation: 公开了一种成像器件，其包括具有形成在其上的感光元件阵列的第一衬底，形成在第一衬底上方的第一导电层，延伸穿过第一衬底的第一导电构件，第一导电构件导电耦合到第一衬底 导电层，形成在第一基板上方的间隔结构，形成在支架结构上方的第二导电层，第二导电层导电耦合到第一导电层，以及位于支架结构之上的电动设备，电动设备 电耦合到第二导电层。 公开了一种制造成像器件的方法，包括提供具有第一导电层的第一衬底和形成在第一衬底上方的感光元件阵列的第一衬底，形成延伸穿过第一衬底的导电构件并与第一导电层 ，在所述第一基板上形成间隔结构，在所述支座结构之上形成图案化导电层，所述图案化导电层导电耦合到所述第一导电层，并且将电动装置导电地连接到位于所述支架结构之上的图案化导电层 。

    Microfeature workpieces having alloyed conductive structures, and associated methods
    6.
    发明授权
    Microfeature workpieces having alloyed conductive structures, and associated methods 有权

    公开(公告)号：US11075146B2

    公开(公告)日：2021-07-27

    申请号：US16722652

    申请日：2019-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Warren M. Farnworth ,  Rick C. Lake ,  William M. Hiatt

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/488 ,  H01L21/768 ,  H01L23/498

    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.

    Methods of processing semiconductor substrates, electrostatic carriers for retaining substrates for processing, and assemblies comprising electrostatic carriers having substrates electrostatically bonded thereto
    8.
    发明授权
    Methods of processing semiconductor substrates, electrostatic carriers for retaining substrates for processing, and assemblies comprising electrostatic carriers having substrates electrostatically bonded thereto 有权
    处理半导体衬底的方法，用于保持用于处理的衬底的静电载体，以及包括具有静电键合衬底的静电载体的组件

    公开(公告)号：US08929052B2

    公开(公告)日：2015-01-06

    申请号：US13921022

    申请日：2013-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Dewali Ray ,  Warren M. Farnworth ,  Kyle K. Kirby

    IPC: H01L21/683

    CPC classification number: H01L21/6833

    Abstract: A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.

    Abstract translation: 处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。 导体从物理接触暴露的导电电极去除。 电介质材料施加在导电电极上。 在静电接触静电载体的同时对衬底进行处理。 在一个实施例中，将导体强制通过电介质材料，该电介质材料被接纳在静电载体的导电电极上，以使导体与导电电极物理接触以将基底静电地接合到静电载体上。 在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。 还公开了用于保持用于加工的基材和这种组件的静电载体。

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