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    Semiconductor die array structure
    2.
    发明授权
    Semiconductor die array structure 有权
    半导体晶片阵列结构

    公开(公告)号：US08884403B2

    公开(公告)日：2014-11-11

    申请号：US12982376

    申请日：2010-12-30

    申请人： Reynaldo Co ,  DeAnn Eileen Melcher ,  Weiping Pan ,  Grant Villavicencio

    发明人： Reynaldo Co ,  DeAnn Eileen Melcher ,  Weiping Pan ,  Grant Villavicencio

    IPC分类号： H01L23/544 ,  H01L21/78 ,  H01L21/683 ,  H01L23/00

    CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/274 ,  H01L2224/83191 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

    摘要： According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

    摘要翻译： 根据本发明，通过两个阶段切割晶片来减小或基本消除晶片位移。 在一些实施例中，在将晶片减薄到规定的模具厚度之前执行第一晶片切割程序; 并且在其他实施例中，在执行第一晶片切割程序之前将晶片减薄到规定的模具厚度。 第一晶片切割程序包括沿着第一组街道切割到大于规定模具厚度的深度，并且可选地沿着第二组街道切割至小于模具厚度的深度。 第一切割过程的结果是一组带状或模具块，每个包括多个连接的模具，其比单独的单个模具更少受到偏移。 在第二晶片切割过程中，通过沿着第二组街道切割来切割模具。 在第一切割过程之后，并且在第二切割过程之前，可以进行对模移的敏感的附加的模具制备程序。

    Electrical interconnect for die stacked in zig-zag configuration
    3.
    发明授权
    Electrical interconnect for die stacked in zig-zag configuration 有权
    用于以锯齿形配置堆叠的管芯的电互连

    公开(公告)号：US08680687B2

    公开(公告)日：2014-03-25

    申请号：US12821454

    申请日：2010-06-23

    申请人： Reynaldo Co ,  Grant Villavicencio ,  Jeffrey S. Leal ,  Simon J. S. McElrea

    发明人： Reynaldo Co ,  Grant Villavicencio ,  Jeffrey S. Leal ,  Simon J. S. McElrea

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L25/0657 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/14

    摘要： A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support. Die in the first tier are electrically interconnected die-to-die, and the tier is electrically connected to a support, by traces of an electrically conductive material contacting interconnect pads on the die and a first set of bond pads on the support. Pillars of a electrically conductive material are formed on a second set of bond pads, and die in the second tier are electrically interconnected die-to-die, and the tier is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the substrate.

    摘要翻译： 模具（或一堆模具）安装在支撑件上并在支撑件上方升高，并且电连接到支撑件中的电路。 导电材料的支柱形成在支撑件的安装侧的一组接合焊盘上，并且升高的模具（或模具的升高堆叠中的至少一个模具）通过电气迹线电连接到支撑件 导电材料将管芯上的互连焊盘接触到支柱，并且通过支柱到支撑件。 而且，以Z字形配置的分层偏移堆叠模组组件，其中第一（下）层的第一方向上的互连边缘和第二层（第二层）堆叠在第一层上的互连边缘， 在与第一方向不同的第二方向上面对电连接到支撑件。 在第一层中的管芯被电连接到芯片之间，并且该层通过导电材料的痕迹电连接到支撑件，导电材料接触管芯上的互连焊盘和支撑件上的第一组接合焊盘。 导电材料的支柱形成在第二组接合焊盘上，并且第二层中的管芯与管芯电连接，并且该层通过迹线导电材料接触互连 模具上的垫子到柱子上，并通过柱子到基底。

    Semiconductor Die Separation Method
    7.
    发明申请
    Semiconductor Die Separation Method 有权
    半导体模具分离方法

    公开(公告)号：US20110101505A1

    公开(公告)日：2011-05-05

    申请号：US12982376

    申请日：2010-12-30

    申请人： Reynaldo Co ,  DeAnn Eileen Melcher ,  Weiping Pan ,  Grant Villavicencio

    发明人： Reynaldo Co ,  DeAnn Eileen Melcher ,  Weiping Pan ,  Grant Villavicencio

    IPC分类号： H01L23/544 ,  H01L23/52

    CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/274 ,  H01L2224/83191 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

    摘要： According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

    摘要翻译： 根据本发明，通过两个阶段切割晶片来减小或基本消除晶片位移。 在一些实施例中，在将晶片减薄到规定的模具厚度之前执行第一晶片切割程序; 并且在其他实施例中，在执行第一晶片切割程序之前将晶片减薄到规定的模具厚度。 第一晶片切割程序包括沿着第一组街道切割到大于规定模具厚度的深度，并且可选地沿着第二组街道切割至小于模具厚度的深度。 第一切割过程的结果是一个或多个模具的阵列，每个芯片或多个模具包括多个连接的模具，其比单独的单个模具更少受到偏移。 在第二晶片切割过程中，通过沿着第二组街道切割来切割模具。 在第一切割过程之后，并且在第二切割过程之前，可以进行对模移的敏感的附加的模具制备程序。

    Semiconductor die separation method
    8.
    发明授权
    Semiconductor die separation method 有权
    半导体芯片分离方法

    公开(公告)号：US07863159B2

    公开(公告)日：2011-01-04

    申请号：US12323288

    申请日：2008-11-25

    申请人： Reynaldo Co ,  DeAnn Eileen Melcher ,  Weiping Pan ,  Grant Villavicencio

    发明人： Reynaldo Co ,  DeAnn Eileen Melcher ,  Weiping Pan ,  Grant Villavicencio

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/274 ,  H01L2224/83191 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

    摘要： According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

    摘要翻译： 根据本发明，通过两个阶段切割晶片来减小或基本消除晶片位移。 在一些实施例中，在将晶片减薄到规定的模具厚度之前执行第一晶片切割程序; 并且在其他实施例中，在执行第一晶片切割程序之前将晶片减薄到规定的模具厚度。 第一晶片切割程序包括沿着第一组街道切割到大于规定模具厚度的深度，并且可选地沿着第二组街道切割至小于模具厚度的深度。 第一切割过程的结果是一组带状或模具块，每个包括多个连接的模具，其比单独的单个模具更少受到偏移。 在第二晶片切割过程中，通过沿着第二组街道切割来切割模具。 在第一切割过程之后，并且在第二切割过程之前，可以进行对模移的敏感的附加的模具制备程序。