公开(公告)号：US20120018876A1

公开(公告)日：2012-01-26

申请号：US12840949

申请日：2010-07-21

申请人： Weng-Jin Wu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Weng-Jin Wu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L21/768 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/11 ,  H01L24/14 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81805

摘要： A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first side of the first die through the first metal bump. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion encircling the second die, and an opening exposing the second region of the first side of the first die. A second metal bump of a second horizontal size is formed on the second region of the first side of the first die and extending into the opening of the dielectric layer. The second horizontal size is greater than the first horizontal size. An electrical component is bonded to the first side of the first die through the second metal bump.

摘要翻译： 一种器件包括具有第一侧和与第一侧相对的第二侧的第一管芯，第一侧包括第一区域和第二区域，以及形成在第一侧面的第一区域上的第一水平尺寸的第一金属凸块 的第一个死亡。 通过第一金属凸块将第二模具结合到第一模具的第一侧。 介电层形成在第一管芯的第一侧上，并且包括直接在第二管芯上方的第一部分，环绕第二管芯的第二部分和暴露第一管芯的第一侧的第二区域的开口。 第二水平尺寸的第二金属凸块形成在第一模具的第一侧的第二区域上并且延伸到电介质层的开口中。 第二个水平尺寸大于第一个水平尺寸。 电子部件通过第二金属凸块接合到第一管芯的第一侧。

公开(公告)号：US20120007048A1

公开(公告)日：2012-01-12

申请号：US13237181

申请日：2011-09-20

申请人： Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

发明人： Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L33/04 ,  H01L33/12 ,  H01L33/32

摘要： A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer.

摘要翻译： 半导体结构包括衬底和与衬底接触的导电载体隧穿层。 导电载体隧穿层包括具有第一带隙的第一III族氮化物（III族氮化物）层，其中第一III族氮化物层具有小于约5nm的厚度; 和具有比第一带隙低的第二带隙的第二III族氮化物层，其中第一III族氮化物层和第二III族氮化物层以交替图案堆叠。 半导体结构在衬底和导电载体 - 隧穿层之间不含III族氮化物层。 半导体结构还包括在导电载体 - 隧穿层上的有源层。

公开(公告)号：US20110309490A1

公开(公告)日：2011-12-22

申请号：US12818890

申请日：2010-06-18

申请人： Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

发明人： Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/13 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/03831 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/93 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/3478 ,  H05K3/4007 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/1082

摘要： A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

摘要翻译： 提供了具有聚合物层的半导体器件及其制造方法。 用于聚合物层表面的两步等离子体处理包括使聚合物层的表面粗糙化并且使污染物松动的第一等离子体工艺，以及使聚合物层更平滑或使聚合物层变得粗糙的第二等离子体工艺。 可以在第一等离子体工艺和第二等离子体工艺之间使用蚀刻工艺，以除去由第一等离子体工艺松动的污染物。 在一个实施方案中，聚合物层通过原子力显微镜（AFM）测量的表面粗糙度在约1％至约8％之间，其表面积差异百分比（SADP）指数和/或具有小于约1的表面污染物 的Ti％，小于约1％的F，小于约1.5％的Sn和小于约0.4％的Pb。

公开(公告)号：US20110277655A1

公开(公告)日：2011-11-17

申请号：US12778867

申请日：2010-05-12

申请人： Francis Ko ,  Chi-Chun Hsieh ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Francis Ko ,  Chi-Chun Hsieh ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B41F33/00

CPC分类号： H01L23/5384 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49883 ,  H01L23/525 ,  H01L23/5328 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

摘要翻译： 形成器件的方法包括在电介质片上印刷导电图案以形成预先印墨的片材，以及将预印墨片材粘合到基片的一侧上。 导电特征包括从衬底的第一主侧延伸到与第一主侧相对的衬底的第二主侧的贯通衬底。 然后施加导电膏以将导电图案电耦合到衬底中的导电特征。

公开(公告)号：US08053900B2

公开(公告)日：2011-11-08

申请号：US12255060

申请日：2008-10-21

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/16106 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/81894 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/12 ,  H01L2224/05552

摘要： An integrated circuit structure includes a semiconductor chip, which further includes a first surface; and a patterned bond pad exposed through the first surface. The patterned bond pad includes a plurality of portions electrically connected to each other, and at least one opening therein. The integrated circuit further includes a dielectric material filled into at least a portion of the at least one opening.

摘要翻译： 集成电路结构包括还包括第一表面的半导体芯片; 以及通过第一表面暴露的图案化接合焊盘。 图案化接合焊盘包括彼此电连接的多个部分和其中的至少一个开口。 集成电路还包括填充到至少一个开口的至少一部分中的电介质材料。

公开(公告)号：US08048723B2

公开(公告)日：2011-11-01

申请号：US12329279

申请日：2008-12-05

申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L21/332

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以形成包括硅片和在硅微细上的冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US08034711B2

公开(公告)日：2011-10-11

申请号：US11964195

申请日：2007-12-26

申请人： Chen-Hua Yu ,  Horng-Huei Tseng

发明人： Chen-Hua Yu ,  Horng-Huei Tseng

IPC分类号： H01L21/4763

CPC分类号： H01L24/05 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/13 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48647 ,  H01L2224/48684 ,  H01L2224/48747 ,  H01L2224/48784 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48781 ,  H01L2224/48681

摘要： A bonding structure and the method of fabricating the same are disclosed. The bonding structure of the invention includes a copper-based pad formed in an insulator layer and a protection layer substantially covering top surface of the copper-based pad. The protection layer is self-aligned formed and the material thereof is selected from a group consisting of metal nitride, copper alloy, copper compounds, and a combination thereof.

摘要翻译： 公开了一种接合结构及其制造方法。 本发明的接合结构包括形成在绝缘体层中的铜基焊盘和基本上覆盖铜基焊盘顶表面的保护层。 保护层是自对准的，其材料选自金属氮化物，铜合金，铜化合物及其组合。

公开(公告)号：US20110241217A1

公开(公告)日：2011-10-06

申请号：US12750100

申请日：2010-03-30

申请人： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/525 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68359 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/14181 ,  H01L2924/01019 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

摘要翻译： 提供了用于堆叠管芯配置的多层互连结构。 在半导体衬底中形成贯通衬底通孔。 将半导体衬底的背面变薄以暴露通过衬底的通孔。 在半导体衬底的背面和贯通衬底通孔的暴露部分之后形成隔离膜。 第一导电元件被形成为电耦合到贯穿衬底通孔中的相应通孔并且在隔离膜上延伸。 可以形成一个或多个附加层的隔离膜和导电元件，其中诸如焊球的连接元件电耦合到最上面的导电元件。

公开(公告)号：US20110210444A1

公开(公告)日：2011-09-01

申请号：US12813212

申请日：2010-06-10

申请人： Shin-Puu Jeng ,  Kim Hong Chen ,  Shang-Yun Hou ,  Chao-Wen Shih ,  Cheng-Chieh Hsieh ,  Chen-Hua Yu

发明人： Shin-Puu Jeng ,  Kim Hong Chen ,  Shang-Yun Hou ,  Chao-Wen Shih ,  Cheng-Chieh Hsieh ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L21/60 ,  H01L23/488

CPC分类号： H01L25/50 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.

摘要翻译： 提供了使用插入器的3D半导体封装。 在一个实施例中，提供了具有电耦合到插入器的第一侧的第一管芯的插入器和电耦合到插入件的第二侧的第二管芯。 插入器电耦合到诸如封装衬底，高密度互连，印刷电路板等的下面的衬底。 衬底具有腔，使得第二管芯位于腔内。 使用空腔可以允许使用更小的导电凸块，从而允许使用更多数量的导电凸块。 散热器可以放置在空腔内以帮助从第二模具散热。

公开(公告)号：US20110186989A1

公开(公告)日：2011-08-04

申请号：US12883950

申请日：2010-09-16

申请人： Yi-Li Hsiao ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chih-Hang Tung ,  Cheng-Chang Wei

发明人： Yi-Li Hsiao ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chih-Hang Tung ,  Cheng-Chang Wei

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L21/44 ,  H01L21/76885 ,  H01L23/49811 ,  H01L23/52 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/80815 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.

摘要翻译： 半导体器件包括覆盖并电连接到焊盘区域的焊料凸块和形成在焊料凸块的至少一部分上的金属盖层。 金属盖层的熔融温度大于焊料凸块的熔化温度。