公开(公告)号：US20070139976A1

公开(公告)日：2007-06-21

申请号：US11620042

申请日：2007-01-04

Applicant: L. deRochemont

Inventor： L. deRochemont

IPC: H02M3/335

CPC classification number: H01F27/2804 ,  B82Y30/00 ,  C04B2235/768 ,  C04B2235/781 ,  H01C7/003 ,  H01C17/003 ,  H01C17/06533 ,  H01F3/00 ,  H01F5/003 ,  H01F27/24 ,  H01F27/29 ,  H01F27/40 ,  H01F41/041 ,  H01F2027/2809 ,  H01G4/10 ,  H01G4/33 ,  H01L23/64 ,  H01L28/10 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01025 ,  H01L2924/01037 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/207 ,  H05K2201/017 ,  H05K2201/0175 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/121 ,  Y10T29/49021

Abstract: A power management module, provides an inductor including one or more electrical conductors disposed around a ferromagnetic ceramic element including one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.50 mol % throughout the ceramic element.

Abstract translation: 电源管理模块提供一种电感器，其包括设置在铁磁性陶瓷元件周围的一个或多个电导体，所述铁磁陶瓷元件包括在整个陶瓷元件中具有小于或等于1.50摩尔％的金属氧化物组成均匀性波动的一种或多种金属氧化物。

公开(公告)号：US20070138633A1

公开(公告)日：2007-06-21

申请号：US11313562

申请日：2005-12-21

Applicant: Daniel Amey ,  William Borland

Inventor： Daniel Amey ,  William Borland

IPC: H01L23/34

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01G4/33 ,  H01L23/50 ,  H01L23/66 ,  H01L27/013 ,  H01L2924/0002 ,  H01L2924/19103 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/162 ,  H05K2201/09763 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: Thick-film capacitors are formed on ceramic interconnect substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are fired at high temperatures.

Abstract translation: 在具有高电容密度和其它所需电气和物理特性的陶瓷互连基板上形成厚膜电容器。 电容器电介质在高温下烧制。

公开(公告)号：US20070077687A1

公开(公告)日：2007-04-05

申请号：US11561261

申请日：2006-11-17

Applicant: Michael Bothe ,  Stefan Morbe

Inventor： Michael Bothe ,  Stefan Morbe

IPC: H01L21/00

CPC classification number: H01L21/00 ,  H01L27/08 ,  H01L28/40 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/162 ,  H05K1/167 ,  H05K3/06 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0187 ,  H05K2201/0347 ,  H05K2201/09036 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0369 ,  H05K2203/063 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49128

Abstract: The present invention relates to a method for producing an electrical subassembly comprising a circuit carrier and at least one passive component which is integrated into the circuit carrier and comprises an electrically functional material. For providing an improved method for manufacturing an electrical subassembly comprising a circuit carrier and at least one passive component integrated into the circuit carrier, the method ensuring a rapid and inexpensive manufacture on the one hand and permitting a high flexibility on the other hand in the selection of the electrically functional materials involved, the method comprising structuring the circuit carrier, at least one recess being created for the passive element; introducing the electrically functional material in a raw state into the recess of the circuit carrier; converting the electrically functional material from the raw state into a final state by supplying energy.

Abstract translation: 本发明涉及一种用于制造电子组件的方法，该电子组件包括电路载体和集成到电路载体中并且包括电功能材料的至少一个无源部件。 为了提供一种用于制造包括电路载体和集成到电路载体中的至少一个无源部件的电子组件的改进方法，该方法一方面确保了快速且便宜的制造，另一方面在选择中允许高灵活性 涉及的电功能材料，所述方法包括构造所述电路载体，为所述无源元件形成至少一个凹部; 将处于原始状态的电功能材料引入电路载体的凹部中; 通过供给能量将电功能材料从原始状态转换成最终状态。

公开(公告)号：US20070063243A1

公开(公告)日：2007-03-22

申请号：US11550798

申请日：2006-10-19

Applicant: Wei-Chun Yang ,  Chien-Wei Chang

Inventor： Wei-Chun Yang ,  Chien-Wei Chang

IPC: H01L27/108 ,  H01L29/94 ,  H01L29/76 ,  H01L31/119

CPC classification number: H05K1/162 ,  H01L21/4867 ,  H01L23/49822 ,  H05K3/4602 ,  H05K2201/09763

Abstract: A new structure is provided to replace the existing common planar capacitor structure used in printed circuit boards. The conventional common planar capacitor structure utilizes a single dielectric layer and embedded capacitors with different capacitances are achieved by adjusting the sizes of the embedded capacitors' conductive terminals. Since general applications usually require capacitors whose capacitance range covers several orders of magnitude, these embedded capacitors have significant differences in terms of their conductive terminals' sizes. This will make the manufacturing process more complicated and difficult. The new structure combines inorganic material having a specific dielectric constant and polymer having another specific dielectric constant into a singulated non-overlapping coplanar capacitor structure that is easy to manufacture and provides better precision.

Abstract translation: 提供了一种新的结构来代替印刷电路板中现有的普通平面电容器结构。 传统的普通平面电容器结构使用单个电介质层，并且通过调整嵌入式电容器的导电端子的尺寸来实现具有不同电容的嵌入式电容器。 由于一般应用通常需要电容范围为几个数量级的电容器，所以这些嵌入式电容器在其导电端子尺寸方面存在显着差异。 这将使制造过程更加复杂和困难。 新结构将具有特定介电常数的无机材料和具有另一特定介电常数的聚合物结合成易于制造和提供更好精度的单个非重叠共面电容器结构。

公开(公告)号：US07178229B2

公开(公告)日：2007-02-20

申请号：US10718044

申请日：2003-11-20

Applicant: William J. Borland ,  Saul Ferguson ,  Diptarka Majumdar ,  Matthew C. Snogren ,  Richard H. Snogren

Inventor： William J. Borland ,  Saul Ferguson ,  Diptarka Majumdar ,  Matthew C. Snogren ,  Richard H. Snogren

IPC: H05K3/30

CPC classification number: H05K3/4679 ,  H01L2224/16225 ,  H05K1/0269 ,  H05K1/092 ,  H05K1/162 ,  H05K1/167 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09063 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/0338 ,  H05K2203/167 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49146 ,  Y10T29/49156

Abstract: Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials.

Abstract translation: 内层板在制造过程中提供高密度基准。 可以使用X射线识别基准，而不蚀刻掉内层面板的部分以暴露基准。

公开(公告)号：US20070030627A1

公开(公告)日：2007-02-08

申请号：US11498070

申请日：2006-08-03

Applicant: Kiyotaka Tsukada

Inventor： Kiyotaka Tsukada

IPC: H01G4/06

CPC classification number: H01G4/33 ,  H01G4/008 ,  H01G4/1218 ,  H05K1/162 ,  H05K3/025 ,  H05K3/143 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09763

Abstract: The present invention provides a thin-film embedded capacitance having a substantial electrostatic capacity per unit area, and a method for manufacturing thereof. A thin film embedded capacitance comprising: a metallic thin-film for wiring made of a metallic material in a non-yield state; the first electrode formed on the film for wiring; a dielectric material layer formed on the first electrode and the film for wiring, at a temperature not lower than ordinary room temperature to lower than a yield temperature of the film for wiring, having a coefficient of thermal expansion lower than that the film for wiring; and the second electrode formed on the dielectric material layer, and a method for manufacturing thereof.

公开(公告)号：US20060282999A1

公开(公告)日：2006-12-21

申请号：US11453387

申请日：2006-06-15

Applicant: Diptarka Majumdar ,  Saul Ferguson

Inventor： Diptarka Majumdar ,  Saul Ferguson

IPC: H01G7/00 ,  H01L21/20

CPC classification number: H05K1/162 ,  H05K1/092 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/017 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2201/09909 ,  Y10T29/435 ,  Y10T29/49155

Abstract: Disclosed is an improved method of embedding capacitors in printed wiring boards (PWB) made from thick film dielectrics and electrodes.

Abstract translation: 公开了一种在由厚膜电介质和电极制成的印刷电路板（PWB）中嵌入电容器的改进方法。

公开(公告)号：US07072168B2

公开(公告)日：2006-07-04

申请号：US10889312

申请日：2004-07-13

Applicant: Yasuyoshi Horikawa ,  Tomoo Yamasaki ,  Kiyoshi Ooi

Inventor： Yasuyoshi Horikawa ,  Tomoo Yamasaki ,  Kiyoshi Ooi

IPC: H01G4/005

CPC classification number: H01G9/012 ,  H01G9/042 ,  H01G9/0425 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/50 ,  H01L2221/68345 ,  H01L2224/05001 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/162 ,  H05K3/205 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/43 ,  H01L2924/00014

Abstract: A capacitor device of the present invention includes a substrate, a float electrode formed on the substrate, a valve metal film formed on the float electrode, a dielectric film formed on the valve metal film by applying an anodic oxidation to a part of the valve metal film, and a pair of electrodes provided in areas overlapping with two different parts of the float electrode on the dielectric film respectively.

Abstract translation: 本发明的电容器装置包括基板，形成在基板上的浮动电极，形成在浮动电极上的阀金属膜，通过对阀金属的一部分施加阳极氧化而形成在阀金属膜上的电介质膜 膜和一对电极，其分别设置在与电极上的浮动电极的两个不同部分重叠的区域中。

公开(公告)号：US20060097344A1

公开(公告)日：2006-05-11

申请号：US11284704

申请日：2005-11-21

Applicant: Michael Casper ,  William Mraz

Inventor： Michael Casper ,  William Mraz

IPC: H01L29/00 ,  H01L23/52

CPC classification number: H01L21/4846 ,  H01L23/15 ,  H01L23/49822 ,  H01L25/16 ,  H01L27/016 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19011 ,  H01Q21/061 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/002 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H01L2924/00

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

公开(公告)号：US20050263874A1

公开(公告)日：2005-12-01

申请号：US11145924

申请日：2005-06-07

Applicant: Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

Inventor： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

IPC: H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K1/16 ,  H05K3/46 ,  H01L21/50 ,  H01L23/58

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49833 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09763 ,  H05K2203/135 ,  H01L2224/05599

Abstract: A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.

Abstract translation: 一种半导体封装，其具有多层互连结构，用于将半导体芯片安装在其顶表面上，其中所述多层互连结构的最上层堆叠结构包括电容器结构，所述电容器结构具有介电层，所述电介质层由混合电沉积层 高介电常数无机填料和绝缘树脂，并且包括用于直接连接具有半导体芯片电极的顶电极和底电极的芯片连接焊盘，从而可以确保互连图案设计的更大自由度，电容器和半导体芯片的接近程度 可以大大改善，并且可以使包装重量更小更轻，其制造方法以及使用该半导体封装的半导体器件。