公开(公告)号：US20110097891A1

公开(公告)日：2011-04-28

申请号：US12906578

申请日：2010-10-18

Applicant: Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Il Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

Inventor： Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Il Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface.

Abstract translation: 制造半导体器件的方法包括制备具有与第一表面相对的第一表面和第二表面的衬底。 在第二表面上形成第一绝缘层。 牺牲层形成在第一绝缘层上。 形成开口以穿透基底并从第一表面延伸到牺牲层的一部分。 第二绝缘层形成在开口的内壁上。 形成塞子以填充开口。 去除牺牲层以通过第二表面暴露插塞的下部。

公开(公告)号：US07875552B2

公开(公告)日：2011-01-25

申请号：US12476793

申请日：2009-06-02

Applicant: Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US20090206464A1

公开(公告)日：2009-08-20

申请号：US12432003

申请日：2009-04-29

Applicant: Hyun-Soo CHUNG ,  Seung-Kwan RYU ,  Ju-Il CHOI ,  Dong-Ho LEE ,  Seong-Deok HWANG

Inventor： Hyun-Soo CHUNG ,  Seung-Kwan RYU ,  Ju-Il CHOI ,  Dong-Ho LEE ,  Seong-Deok HWANG

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01028 ,  H01L2224/03

Abstract: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

Abstract translation: 提供制造半导体芯片的方法，通过该方法形成的半导体芯片和具有半导体芯片的芯片堆叠封装。 一个实施例规定了一种方法，其包括图案化半导体衬底的划线区域以形成与半导体衬底的芯片区域的边缘间隔开的半导体支柱。

公开(公告)号：US20080230923A1

公开(公告)日：2008-09-25

申请号：US12051619

申请日：2008-03-19

Applicant: Cha-Jea JO ,  Myung-Kee CHUNG ,  Nam-Seog KIM ,  In-Young LEE ,  Seok-Ho KIM ,  Ho-Jin LEE ,  Ju-Il CHOI ,  Chang-Woo SHIN

Inventor： Cha-Jea JO ,  Myung-Kee CHUNG ,  Nam-Seog KIM ,  In-Young LEE ,  Seok-Ho KIM ,  Ho-Jin LEE ,  Ju-Il CHOI ,  Chang-Woo SHIN

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract translation: 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US20160099201A1

公开(公告)日：2016-04-07

申请号：US14873453

申请日：2015-10-02

Applicant: Ju-il Choi ,  Atsushi Fujisaki ,  Byung-lyul Park ,  Ji-soon Park ,  Joo-hee Jang ,  Jeong-gi Jin

Inventor： Ju-il Choi ,  Atsushi Fujisaki ,  Byung-lyul Park ,  Ji-soon Park ,  Joo-hee Jang ,  Jeong-gi Jin

IPC: H01L23/498 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11825 ,  H01L2224/11906 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13552 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/014 ,  H01L2924/01074

Abstract: An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied.

Abstract translation: 集成电路器件包括半导体结构，穿透半导体结构的穿透硅通孔（TSV）结构和连接到TSV结构的连接端子。 金属覆盖层包括覆盖连接端子的底表面的平坦封盖部分和与扁平封盖部分整体连接并部分覆盖连接端子的侧壁的楔形封盖部分。 金属覆盖层可以通过电镀工艺形成，其中连接端子与金属冲击电镀溶液接触，同时施加脉冲型电流。

公开(公告)号：US09082680B2

公开(公告)日：2015-07-14

申请号：US13535766

申请日：2012-06-28

Applicant: Ju-Il Choi ,  Jeong-Gi Jin ,  Ui-Hyoung Lee ,  Hyung-Seok Kim ,  Jeong-Woo Park

Inventor： Ju-Il Choi ,  Jeong-Gi Jin ,  Ui-Hyoung Lee ,  Hyung-Seok Kim ,  Jeong-Woo Park

IPC: H05K1/16 ,  H05K1/18 ,  H01L23/00 ,  H05K3/34 ,  B23K1/00 ,  H01L25/065 ,  H01L25/10 ,  H05K3/40 ,  H01L23/31

CPC classification number: H01L24/16 ,  B23K1/0016 ,  B23K2101/42 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/13686 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/181 ,  H05K3/3442 ,  H05K3/3489 ,  H05K3/4007 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/053 ,  H01L2924/00012

Abstract: The inventive concept provides methods for inhibiting the formation of one or more oxides on metal bumps during the formation of solder joint structures and solder joint structures including one or more preservative films. In some embodiments, the solder joint structure includes a metal bump having a preservative film disposed on the surface thereof.

Abstract translation: 本发明构思提供了在形成包括一个或多个防腐膜的焊接结构和焊点结构期间，抑制在金属凸块上形成一种或多种氧化物的方法。 在一些实施例中，焊点结构包括具有设置在其表面上的防腐膜的金属凸块。

公开(公告)号：US20150137387A1

公开(公告)日：2015-05-21

申请号：US14543688

申请日：2014-11-17

Applicant: Ju-il CHOI ,  Kun-sang PARK ,  Son-kwan HWANG ,  Ji-soon PARK ,  Byung-lyul PARK

Inventor： Ju-il CHOI ,  Kun-sang PARK ,  Son-kwan HWANG ,  Ji-soon PARK ,  Byung-lyul PARK

IPC: H01L23/532 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/53238 ,  H01L23/53266 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.

Abstract translation: 集成电路（IC）装置包括具有贯穿其至少一部分的通孔的半导体衬底，通孔中的导电结构，与导电结构相邻的导电阻挡层; 以及插入在半导体衬底和导电阻挡层之间的通孔绝缘层。 导电阻挡层可以包括在导电阻挡层和通孔绝缘层之间氧化的外部部分，并且导电阻挡层的氧化外部部分可以基本上围绕导电阻挡层的剩余部分。

公开(公告)号：US20130000978A1

公开(公告)日：2013-01-03

申请号：US13535766

申请日：2012-06-28

Applicant: Ju-Il Choi ,  Jeong-Gi Jin ,  Ui-Hyoung Lee ,  Hyung-Seok Kim ,  Jeong-Woo Park

Inventor： Ju-Il Choi ,  Jeong-Gi Jin ,  Ui-Hyoung Lee ,  Hyung-Seok Kim ,  Jeong-Woo Park

IPC: H01R4/02

CPC classification number: H01L24/16 ,  B23K1/0016 ,  B23K2101/42 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/13686 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/181 ,  H05K3/3442 ,  H05K3/3489 ,  H05K3/4007 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/053 ,  H01L2924/00012

Abstract: The inventive concept provides methods for inhibiting the formation of one or more oxides on metal bumps during the formation of solder joint structures and solder joint structures including one or more preservative films. In some embodiments, the solder joint structure includes a metal bump having a preservative film disposed on the surface thereof.

Abstract translation: 本发明构思提供了在形成包括一个或多个防腐膜的焊接结构和焊点结构期间，抑制在金属凸块上形成一种或多种氧化物的方法。 在一些实施例中，焊点结构包括具有设置在其表面上的防腐膜的金属凸块。

公开(公告)号：US20120133041A1

公开(公告)日：2012-05-31

申请号：US13303255

申请日：2011-11-23

Applicant: Jae-hyun Phee ,  Uihyouong Lee ,  Ju-il Choi ,  Jung-Hwan Kim

Inventor： Jae-hyun Phee ,  Uihyouong Lee ,  Ju-il Choi ,  Jung-Hwan Kim

IPC: H01L23/498

CPC classification number: H01L29/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05571 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Some embodiments provide a semiconductor device including a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion that supports the protruding portion. Methods of fabricating the same are also provided.

Abstract translation: 一些实施例提供包括具有第一表面和相对的第二表面的基板的半导体器件。 电极在衬底内朝向第一表面延伸并且具有从第一表面延伸的突出部分。 支撑部分从基板的第一表面延伸到支撑突出部分的突出部分的侧壁。 还提供了制造方法。

公开(公告)号：US20120083097A1

公开(公告)日：2012-04-05

申请号：US13187760

申请日：2011-07-21

Applicant: Ju-il Choi ,  Kyu-Ha Lee ,  Jae-Hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

Inventor： Ju-il Choi ,  Kyu-Ha Lee ,  Jae-Hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/486 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/02372 ,  H01L2224/1146 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2224/81 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.

Abstract translation: 提供一种形成半导体封装的方法，包括提供具有第一侧和相对的第二侧的衬底，并提供具有多个半导体芯片的晶片，每个半导体芯片具有导电焊盘，其中至少一个衬底 并且晶片包括种子图案。 衬底的第一面被接合到晶片，其中导电焊盘定位成与衬底的第一侧相邻，并且种子图案位于导电焊盘和衬底的第一侧之间。 然后从衬底的第二侧穿透衬底以形成通孔以暴露种子图案。 使用种子图案作为种子在通孔中形成贯通电极。 还提供了相应的设备。