公开(公告)号：US20080128905A1

公开(公告)日：2008-06-05

申请号：US11950251

申请日：2007-12-04

Applicant: In-Young LEE ,  Dong-Ho LEE ,  Nam-Seog KIM ,  Hyun-Soo CHUNG ,  Ho-Jin LEE ,  Myeong-Soo PARK

Inventor： In-Young LEE ,  Dong-Ho LEE ,  Nam-Seog KIM ,  Hyun-Soo CHUNG ,  Ho-Jin LEE ,  Myeong-Soo PARK

IPC: H01L23/488 ,  H01L21/44

CPC classification number: H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

Abstract translation: 提供了其中在晶片级应用再分配处理的晶片级芯片级封装，其制造方法以及包括晶片级芯片级封装的半导体芯片模块。 晶片级芯片级封装包括具有接合焊盘的半导体芯片，设置在半导体芯片上以暴露焊盘的第一绝缘层，设置在暴露的焊盘和第一绝缘层上的再分配线，牺牲层 设置在所述再分配线的再分配衬垫的下方，设置在所述再分配线上的第二绝缘层，以暴露所述再分配衬垫并且包括设置在所述牺牲层旁边的裂纹诱导孔，以及附接到所述再分布衬垫的外部连接端子。

公开(公告)号：US20150137326A1

公开(公告)日：2015-05-21

申请号：US14463645

申请日：2014-08-19

Applicant: Pil-Kyu KANG ,  Byung Lyul PARK ,  SungHee KANG ,  TAESEONG KIM ,  TAEYEONG KIM ,  KWANGJIN MOON ,  Jae-Hwa PARK ,  SUKCHUL BANG ,  Seongmin SON ,  JIN HO AN ,  Ho-Jin LEE ,  JEONGGI JIN

Inventor： Pil-Kyu KANG ,  Byung Lyul PARK ,  SungHee KANG ,  TAESEONG KIM ,  TAEYEONG KIM ,  KWANGJIN MOON ,  Jae-Hwa PARK ,  SUKCHUL BANG ,  Seongmin SON ,  JIN HO AN ,  Ho-Jin LEE ,  JEONGGI JIN

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

Abstract translation: 半导体器件包括具有彼此相对的顶表面和底表面的半导体衬底，设置在半导体衬底的顶表面上并且包括集成电路的层间介质层，设置在层间介电层上的金属间介电层 并且包括电连接到集成电路的至少一个金属互连，设置在金属间电介质层上的上部电介质层，贯穿金属间介电层的贯通电极，层间绝缘层和半导体基板， 所述通孔电介质层包围所述贯通电极，并且使所述通孔与所述半导体基板电绝缘。 通孔电介质层包括上电介质层和层间电介质层之间的一个或多个气隙。

公开(公告)号：US20130210222A1

公开(公告)日：2013-08-15

申请号：US13758239

申请日：2013-02-04

Applicant: Ho-Jin LEE ,  Kyu-ha LEE ,  Gilheyun CHOI ,  YongSoon CHOI ,  Pil-Kyu KANG ,  Byung-Lyul PARK ,  Hyunsoo CHUNG

Inventor： Ho-Jin LEE ,  Kyu-ha LEE ,  Gilheyun CHOI ,  YongSoon CHOI ,  Pil-Kyu KANG ,  Byung-Lyul PARK ,  Hyunsoo CHUNG

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/768 ,  H01L21/02271 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer.

Abstract translation: 在一个实施例中，该方法包括在基层中形成导电通孔结构。 基层具有第一表面和第二表面，并且第二表面与第一表面相对。 该方法还包括去除基底层的第二表面以暴露导电通路结构，使得导电通孔结构从第二表面突出，并且在第二表面上形成第一下绝缘层，使得导电通孔的端表面 结构保持由第一下绝缘层暴露。

公开(公告)号：US20130200525A1

公开(公告)日：2013-08-08

申请号：US13718580

申请日：2012-12-18

Applicant: Ho-Jin LEE ,  Pil-Kyu KANG ,  Kyu-Ha LEE ,  Byung-Lyul PARK ,  Hyun-Soo CHUNG ,  Gil-Heyun CHOI

Inventor： Ho-Jin LEE ,  Pil-Kyu KANG ,  Kyu-Ha LEE ,  Byung-Lyul PARK ,  Hyun-Soo CHUNG ,  Gil-Heyun CHOI

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.

Abstract translation: 一种半导体器件，包括下层，在下层的第一侧上的绝缘层，绝缘层中的互连结构，下层中的通孔结构。 通孔结构突出到绝缘层和互连结构中。

公开(公告)号：US20080230923A1

公开(公告)日：2008-09-25

申请号：US12051619

申请日：2008-03-19

Applicant: Cha-Jea JO ,  Myung-Kee CHUNG ,  Nam-Seog KIM ,  In-Young LEE ,  Seok-Ho KIM ,  Ho-Jin LEE ,  Ju-Il CHOI ,  Chang-Woo SHIN

Inventor： Cha-Jea JO ,  Myung-Kee CHUNG ,  Nam-Seog KIM ,  In-Young LEE ,  Seok-Ho KIM ,  Ho-Jin LEE ,  Ju-Il CHOI ,  Chang-Woo SHIN

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract translation: 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US20110157049A1

公开(公告)日：2011-06-30

申请号：US12976511

申请日：2010-12-22

Applicant: Ho-Jin LEE ,  Jeong-Seok Lee ,  Eun-Hwa Lee ,  Yu-Dong Bae ,  Jin-Hyoung Park

Inventor： Ho-Jin LEE ,  Jeong-Seok Lee ,  Eun-Hwa Lee ,  Yu-Dong Bae ,  Jin-Hyoung Park

IPC: G08B6/00 ,  G06F3/041

CPC classification number: G06F3/016 ,  G06F3/041 ,  G06F2203/014 ,  G08B6/00

Abstract: Provided is an apparatus and method for generating vibrations in a wireless terminal, in which vibrations of strengths corresponding to respective regions are generated by using a plurality of piezos. The apparatus includes a plurality of piezos, a touch screen portion including a plurality of regions, and a controller for, upon detection of a touch on a predetermined region among the plurality of regions of the touch screen portion, generating vibrations of strengths according to power frequencies and power polarities of the plurality of piezos with respect to the touched region.

Abstract translation: 提供了一种用于在无线终端中产生振动的装置和方法，其中通过使用多个压电体产生对应于各个区域的强度的振动。 该装置包括多个压电体，包括多个区域的触摸屏部分和控制器，用于在检测到触摸屏部分的多个区域中的预定区域上的触摸时，根据功率产生强度的振动 多个压电体相对于触摸区域的频率和功率极性。

公开(公告)号：US20110149837A1

公开(公告)日：2011-06-23

申请号：US12938522

申请日：2010-11-03

Applicant: Hee-Wook KIM ,  Kunseok KANG ,  Do-Seob AHN ,  Ho-Jin LEE

Inventor： Hee-Wook KIM ,  Kunseok KANG ,  Do-Seob AHN ,  Ho-Jin LEE

IPC: H04B7/204

CPC classification number: H04B7/18545

Abstract: Provided is mobile satellite communication method and apparatus. The satellite communication method includes detecting a location of a terminal, determining a signal transmission scheme for the terminal using the terminal location, determining a subcarrier region to transmit a signal to the terminal using the location of the terminal, and communicating with the terminal using the determined signal transmission scheme and the determined subcarrier region.

Abstract translation: 提供了移动卫星通信方法和装置。 卫星通信方法包括检测终端的位置，使用终端位置确定终端的信号传输方案，使用终端的位置确定子载波区域向终端发送信号，并使用 确定的信号传输方案和确定的子载波区域。

公开(公告)号：US20090085224A1

公开(公告)日：2009-04-02

申请号：US12244591

申请日：2008-10-02

Applicant: Ju-Il CHOI ,  Hyun-Soo CHUNG ,  In-Young LEE ,  Ho-Jin LEE ,  Son-Kwan HWANG

Inventor： Ju-Il CHOI ,  Hyun-Soo CHUNG ,  In-Young LEE ,  Ho-Jin LEE ,  Son-Kwan HWANG

IPC: H01L23/538 ,  H01L21/58

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/29101 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06575 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2924/00

Abstract: Provided is a stack-type semiconductor package including a base chip having a circuit formed on one of its surfaces, at least one stack chip having a circuit stacked on the base chip, an adhesive interposed between the base chip and the stack chip, and signal transmission members formed along a lateral surface of the stack chip. The fabrication process of this stack-type semiconductor package may be simplified and the number of process operations may be lessened, thereby reducing the production time and cost. Also, a state of electrical contact of a terminal with a signal transmission member may be solidified, thereby improving the reliability of the stack-type semiconductor package. Furthermore, new post-type signal transmission members are adopted instead of wires or electrodes so that the structural stability and productivity of the stack-type semiconductor package may be markedly enhanced.

Abstract translation: 提供了一种堆叠型半导体封装，其包括具有形成在其一个表面上的电路的基底芯片，具有堆叠在基底芯片上的电路的至少一个堆叠芯片，插入在基底芯片和堆叠芯片之间的粘合剂，以及信号 传输构件沿着堆叠芯片的侧表面形成。 可以简化该堆叠型半导体封装的制造工艺，并且可以减少工艺操作的数量，从而减少生产时间和成本。 此外，端子与信号传输部件的电接触的状态可以被固化，从而提高堆叠型半导体封装的可靠性。 此外，采用新的后置型信号传输构件代替线或电极，从而可以显着提高堆叠型半导体封装的结构稳定性和生产率。

公开(公告)号：US20090008790A1

公开(公告)日：2009-01-08

申请号：US12132925

申请日：2008-06-04

Applicant: Ho-Jin LEE ,  Nam-Seog KIM ,  Yong-Chai KWON ,  Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG

Inventor： Ho-Jin LEE ,  Nam-Seog KIM ,  Yong-Chai KWON ,  Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05561 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/00014

Abstract: A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.

Abstract translation: 公开了一种具有通孔的半导体器件及其制造方法。 在一个实施例中，半导体器件包括形成在半导体衬底上的第一绝缘层。 具有用于露出第一绝缘层的一部分的第一孔的布线层形成在第一绝缘层上。 第二绝缘层形成在布线层的上部和第一孔中。 具有第二孔径以暴露第二绝缘层的一部分的导电焊盘形成在第二绝缘层上。 通过第一和第二绝缘层和半导体衬底的上部形成宽度比第一和第二孔的宽度窄的通孔。 在通孔中形成贯通电极。