公开(公告)号：US08399989B2

公开(公告)日：2013-03-19

申请号：US11461416

申请日：2006-07-31

申请人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

发明人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05683 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48673 ,  H01L2224/48683 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.

摘要翻译： 一种电路部件，包括半导体衬底，所述半导体衬底上的衬垫，在侧壁上的含钽层和所述焊盘的底表面，所述半导体衬底上的钝化层，所述钝化层中的露出所述衬垫的开口， 由所述开口暴露在所述垫上的含钛层，以及在所述含钛层上方的金层。

公开(公告)号：US07582556B2

公开(公告)日：2009-09-01

申请号：US11426317

申请日：2006-06-26

申请人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Ke-Hung Chen

发明人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC分类号： H01L21/4763

CPC分类号： H01L24/12 ,  H01L21/76801 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/53295 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45176 ,  H01L2224/45183 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2224/05599

摘要： A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.

摘要翻译： 电路结构包括半导体衬底，半导体衬底上的第一和第二金属柱，半导体衬底上的绝缘层，并覆盖第一和第二金属柱，第一和第二金属柱上的第一和第二凸块或绝缘层 。 第一和第二金属柱的高度为20至300微米，其最大水平尺寸与其高度之比小于4.第一凸起的中心与第二凸起的中心之间的距离 在10和250微米之间。

公开(公告)号：US08304907B2

公开(公告)日：2012-11-06

申请号：US12001676

申请日：2007-12-12

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/11 ,  H01L21/768 ,  H01L21/76804 ,  H01L21/76838 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/60 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2224/05552 ,  H01L2924/00

摘要： The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

摘要翻译： 本发明在完成的半导体晶片的顶部上添加一层或多层厚的聚合物电介质和一层或多层厚的宽金属线，后钝化。 厚的宽金属线可用于长信号路径，也可用于电力总线或电源平面，时钟分配网络，关键信号和I / O焊盘的重新分配。

公开(公告)号：US08242601B2

公开(公告)日：2012-08-14

申请号：US12464896

申请日：2009-05-13

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L21/76801 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

摘要翻译： 本发明提供一种半导体芯片，其包括半导体衬底，该半导体衬底包括MOS器件，在所述半导体衬底上的互连结构以及在所述MOS器件上方的金属凸块，其中所述金属凸块具有大于50重量％的金， 介于8和50微米之间。

公开(公告)号：US08198729B2

公开(公告)日：2012-06-12

申请号：US11183648

申请日：2005-07-18

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Mou-Shiung Lin

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Mou-Shiung Lin

IPC分类号： H01L23/48

CPC分类号： H01L24/02 ,  H01L23/5227 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05085 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19042 ,  H01L2224/29075

摘要： A semiconductor chip or wafer includes a passivation layer, a pad and a bump. The pad is exposed by an opening in the passivation layer. The bump is connected to the pad, wherein the area of the connection between the pad and the bump is larger than 30,000 μm2.

摘要翻译： 半导体芯片或晶片包括钝化层，焊盘和凸块。 该焊盘由钝化层中的开口暴露。 凸块连接到焊盘，其中焊盘和凸块之间的连接的面积大于30,000μm2。

公开(公告)号：US20110266669A1

公开(公告)日：2011-11-03

申请号：US13181255

申请日：2011-07-12

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin ,  Hsin-Jung Lo

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin ,  Hsin-Jung Lo

IPC分类号： H01L23/532

CPC分类号： H01L24/73 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05155 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05553 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/48463 ,  H01L2224/48477 ,  H01L2224/4943 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/4554

摘要： The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns

摘要翻译： 本发明提供一种包括在所述钝化层上的互连结构的半导体芯片。 互连结构包括连接到由钝化层中的开口暴露的第二接触焊盘的第一接触焊盘。 金属凸块位于第一接触焊盘上并且在多个半导体器件上，其中金属凸块具有超过50重量％的金并且具有在8和50微米之间的高度

公开(公告)号：US08021918B2

公开(公告)日：2011-09-20

申请号：US11864935

申请日：2007-09-29

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Chien-Kang Chou

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/552 ,  H01L21/76816 ,  H01L21/76873 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L27/0251 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48764 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/01039 ,  H01L2924/00 ,  H01L2224/05552

摘要： An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

摘要翻译： 集成电路芯片包括硅衬底，位于所述硅衬底中或之上的第一电路，位于所述硅衬底中或之上的第二电路器件，所述硅衬底上的电介质结构，所述电介质结构中的第一互连结构，第一衬垫 通过所述第一互连结构连接到所述电压调节器的所述第一节点，所述电介质结构中的第二互连结构，通过所述第二互连结构连接到所述内部电路的所述第一节点的第二焊盘，所述电介质结构上的钝化层， 其中所述钝化层中的多个开口暴露所述第一和第二焊盘，以及在所述钝化层上方以及所述第一和第二焊盘之上的第三互连结构。

公开(公告)号：US08018060B2

公开(公告)日：2011-09-13

申请号：US12014812

申请日：2008-01-16

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L29/72

CPC分类号： H01L23/5223 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/01019 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/014

摘要： A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

摘要翻译： 描述了用于形成后钝化金属结构的系统和方法。 金属互连和高质量的电气部件，例如电感器，变压器，电容器或电阻器形成在钝化层上，或者在钝化层上的厚层聚合物上。

公开(公告)号：US20110215469A1

公开(公告)日：2011-09-08

申请号：US13108811

申请日：2011-05-16

申请人： Hsin-Jung Lo ,  Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Hsin-Jung Lo ,  Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L24/11 ,  H01L21/2885 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48844 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/01004

摘要： A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

摘要翻译： 一种用于制造电路部件的方法，包括在衬底上沉积第一金属层; 在所述第一金属层上形成第一图案界定层，所述第一图案限定层中的第一开口露出所述第一金属层; 在由所述第一开口暴露的所述第一金属层上沉积第二金属层; 去除所述第一图案限定层; 在所述第二金属层上形成第二图案界定层，所述第二图案限定层中的第二开口暴露所述第二金属层; 在由所述第二开口露出的所述第二金属层上沉积第三金属层; 去除所述第二图案限定层; 去除不在所述第二金属层下方的所述第一金属层; 以及在所述第二金属层上形成聚合物层，其中所述第三金属层用作结合到外部电路的金属凸块。

公开(公告)号：US08004083B2

公开(公告)日：2011-08-23

申请号：US11864927

申请日：2007-09-29

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Chien-Kang Chou

IPC分类号： H01L23/52

CPC分类号： H01L23/552 ,  H01L21/76816 ,  H01L21/76873 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L27/0251 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48764 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/01039 ,  H01L2924/00 ,  H01L2224/05552

摘要： An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.