公开(公告)号：US20160118333A1

公开(公告)日：2016-04-28

申请号：US14971627

申请日：2015-12-16

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L23/528 ,  H01L21/768 ,  H01L25/00 ,  H01L23/31 ,  H01L25/16 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L23/528 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/03334 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00014

Abstract: A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, and dicing the first KGU and KGD from the first redistribution interconnect structure. The method further includes the steps of testing a unit of the second redistribution interconnect structure to determine a second KGU of the second redistribution interconnect structure and disposing first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：提供第一生产线，提供第二生产线，以及使用第一生产线形成第一再分配互连结构，同时使用第二生产线形成第二再分布互连结构。 该方法还包括以下步骤：测试第一再分布互连结构的第一单元以确定第一已知良好单元（KGU），在第一再分配互连结构的第一KGU上设置已知的良好半导体管芯（KGD），以及切割 第一个再分配互连结构的KGU和KGD。 该方法还包括以下步骤：测试第二再分配互连结构的单元以确定第二再分布互连结构的第二KGU，并且将第一再分布互连结构的第一KGU和KGD布置在第二再分配互连结构的第二KGU上 。

公开(公告)号：US20150348936A1

公开(公告)日：2015-12-03

申请号：US14721677

申请日：2015-05-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Byung Joon Han ,  Rajendra D. Pendse ,  Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Linda Pei Ee Chua

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component.

Abstract translation: 半导体器件具有第一部件。 模块化互连结构被布置成与第一部件相邻。 在第一组件和模块化互连结构上形成第一互连结构。 在第一组件，模块化互连结构和第一互连结构上形成屏蔽层。 屏蔽层为封闭的半导体器件提供防止EMI，RFI或其他器件间干扰的保护，无论是内部产生还是从外部半导体器件产生。 屏蔽层电连接到外部低阻抗接地点。 第二部件邻近第一部件设置。 第二组件包括无源设备。 LC电路包括第一部件和第二部件。 将半导体管芯设置成与第一部件相邻。 导电粘合剂设置在模块化互连结构之上。 模块化互连结构包括小于第一部件的高度的高度。

公开(公告)号：US20150179616A1

公开(公告)日：2015-06-25

申请号：US14624136

申请日：2015-02-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/568 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/82

Abstract: A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices.

Abstract translation: 半导体器件具有形成在衬底上的第一构建互连结构。 第一构建互连结构包括绝缘层和形成在绝缘层上的导电层。 垂直互连结构和半导体管芯设置在第一堆积互连结构之上。 半导体管芯，第一堆叠互连结构和衬底设置在载体上。 密封剂沉积在半导体管芯，第一堆积互连结构和衬底上。 第二堆积互连结构形成在密封剂上。 第二堆叠互连结构通过垂直互连结构电连接到第一堆叠互连结构。 衬底提供结构支撑并防止形成第一和第二堆积互连结构期间的翘曲。 在形成第二堆积互连结构之后去除衬底。 绝缘层的一部分被去除，暴露出导电层用于随后堆叠的半导体器件的电互连。

公开(公告)号：US09064936B2

公开(公告)日：2015-06-23

申请号：US13832333

申请日：2013-03-15

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Seung Wook Yoon

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0613 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

Abstract translation: 半导体器件具有沉积在半导体管芯的第一表面上并且围绕半导体管芯的密封剂。 在半导体管芯的与第一表面相对的第二表面上形成第一绝缘层。 导电层形成在第一绝缘层上。 通过半导体管芯的覆盖区外的密封剂形成互连结构，并电连接到导电层。 第一绝缘层包括光学透明或半透明材料。 半导体管芯包括被配置为接收穿过第一绝缘层的外部刺激的传感器。 在半导体管芯的第一表面上形成第二绝缘层。 通过半导体管芯的覆盖区外的第一绝缘层形成导电通孔。 多个层叠的半导体器件通过互连结构电连接。

公开(公告)号：US20150145126A1

公开(公告)日：2015-05-28

申请号：US14564427

申请日：2014-12-09

Applicant: STATS CHIPPAC, LTD.

Inventor： Yaojian Lin ,  II Kwon Shim ,  Seng Guan Chow

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.

Abstract translation: 半导体器件具有在指定用于凸块形成的位置中安装到临时衬底的应力释放缓冲器。 应力消除缓冲器可以是多层复合材料，例如第一顺应层，在第一柔性层上形成的硅层，以及形成在硅层上的第二柔性层。 半导体管芯也安装在临时衬底上。 应力消除缓冲器可以比半导体管芯更薄。 密封剂沉积在半导体管芯和应力释放缓冲器之间。 移除临时衬底。 在半导体管芯，密封剂和应力释放缓冲器上形成互连结构。 互连结构电连接到半导体管芯。 可以在应力消除缓冲器和密封剂上形成加强层。 可以在应力消除缓冲器内形成包含有源器件，无源器件，导电层和电介质层的电路层。

公开(公告)号：US20150115465A1

公开(公告)日：2015-04-30

申请号：US14329464

申请日：2014-07-11

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Hin Hwa Goh ,  Il Kwon Shim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/485 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24155 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/82

Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

Abstract translation: 半导体器件具有基板。 通过衬底形成导电通孔。 在衬底的第一表面上形成多个第一接触焊盘。 在衬底的第二表面上形成多个第二接触焊盘。 在衬底的第二表面上形成虚拟图案。 在衬底的侧壁中形成凹陷。 通过基板形成开口。 密封剂沉积在开口中。 在衬底的第二表面上形成绝缘层。 在绝缘层中形成有虚设的开口。 半导体管芯与衬底相邻地设置。 密封剂沉积在半导体管芯和衬底上。 衬底的第一表面包括大于衬底的第二表面的宽度的宽度。

公开(公告)号：US08980691B2

公开(公告)日：2015-03-17

申请号：US13931397

申请日：2013-06-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/24 ,  H01L23/02 ,  H01L23/52 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device includes a substrate having an insulating layer and a conductive layer embedded in the insulating layer. The conductive layer is patterned to form conductive pads or conductive pillars. The substrate includes a first encapsulant formed over the conductive layer. A first opening is formed through insulating layer and first encapsulant using a stamping process or laser direct ablation. The substrate is separated into individual units, which are mounted to a carrier. A semiconductor die is disposed in the first opening in the substrate. A second encapsulant is deposited over the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and substrate. An opening is formed through the second encapsulant and through the insulating layer to expose the conductive layer. A bump is formed in the second opening over the conductive layer outside a footprint of the semiconductor die.

Abstract translation: 半导体器件包括具有绝缘层和嵌入绝缘层中的导电层的衬底。 将导电层图案化以形成导电焊盘或导电柱。 衬底包括形成在导电层上的第一密封剂。 通过使用冲压工艺或激光直接烧蚀的绝缘层和第一密封剂形成第一开口。 将基板分离成单独的单元，其安装到载体上。 半导体管芯设置在衬底的第一开口中。 第二密封剂沉积在半导体管芯和衬底上。 在半导体管芯和衬底上形成互连结构。 通过第二密封剂形成开口并穿过绝缘层以露出导电层。 在半导体管芯的覆盖区外的导电层上的第二开口中形成凸块。

公开(公告)号：US08975980B2

公开(公告)日：2015-03-10

申请号：US14018282

申请日：2013-09-04

Applicant: STATS ChipPAC, Ltd.

Inventor： Kai Liu ,  Robert C. Frye ,  Yaojian Lin

IPC: H01P3/08 ,  H01F19/00 ,  H03H7/42 ,  H03H7/09 ,  H03H7/01 ,  H01L49/02

CPC classification number: H03H7/422 ,  H01L28/10 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/42

Abstract: A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.

Abstract translation: 带通滤波器具有多个频带信道，每个频带信道包括具有耦合到第一平衡端口的第一端子的第一电感器和耦合到第二平衡端口的第二端子。 第一电容器耦合在第一电感器的第一和第二端子之间。 第二电感器具有耦合到第一不平衡端口的第一端子和耦合到第二不平衡端口的第二端子。 第二电感器设置在第一电感器的第一距离内以引起磁耦合。 第二电容器耦合在第二电感器的第一和第二端子之间。 第三电感器设置在第一电感器的第二距离内并且在第二电感器的第三距离内，以引起磁耦合。 第二电容器耦合在第三电感器的第一和第二端子之间。

公开(公告)号：US20150028471A1

公开(公告)日：2015-01-29

申请号：US13950122

申请日：2013-07-24

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu

IPC: H01L23/498 ,  H01L21/66

CPC classification number: H01L23/49811 ,  H01L22/12 ,  H01L22/20 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor die and an encapsulant formed over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A plurality of conductive vias is formed through the first insulating layer. A conductive pad is formed over the encapsulant. An interconnect structure is formed over the semiconductor die and encapsulant. A first opening is formed in the encapsulant to expose the conductive vias. The conductive vias form a conductive via array. The conductive via array is inspected through the first opening to measure a dimension of the first opening and determine a position of the first opening. The semiconductor device is adjusted based on a position of the conductive via array. A conductive material is formed in the first opening over the conductive via array.

Abstract translation: 半导体器件包括形成在半导体管芯的第一表面上并围绕半导体管芯的半导体管芯和密封剂。 在半导体管芯的与第一表面相对的第二表面上形成第一绝缘层。 通过第一绝缘层形成多个导电孔。 在密封剂上形成导电焊盘。 在半导体管芯和密封剂上形成互连结构。 在密封剂中形成第一开口以暴露导电通孔。 导电通孔形成导电通孔阵列。 通过第一开口检查导电通孔阵列以测量第一开口的尺寸并确定第一开口的位置。 基于导电通孔阵列的位置来调整半导体器件。 在导电通孔阵列上的第一开口中形成导电材料。

公开(公告)号：US20140339683A1

公开(公告)日：2014-11-20

申请号：US14449869

申请日：2014-08-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng ,  Xusheng Bao

IPC: H01L23/544 ,  H01L23/28 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14135 ,  H01L2224/221 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract translation: 多个半导体管芯安装到临时载体上。 密封剂沉积在半导体管芯和载体上。 密封剂的一部分被指定为模具之间的锯道，并且密封剂的一部分被指定为围绕密封剂的周边的基底边缘。 载体被移除。 在模具，锯条和基板边缘上形成第一绝缘层。 在第一绝缘层上形成第一导电层。 在第一导电层和第一绝缘层上形成第二绝缘层。 通过第一绝缘层和锯条将密封剂分离，以分离半导体管芯。 可以在锯条的相对侧的第一绝缘层中形成通道或网状图案，或者第一绝缘层覆盖整个锯条和半导体管芯周围的成型区域。