公开(公告)号：US20240038646A1

公开(公告)日：2024-02-01

申请号：US17878647

申请日：2022-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hao-Cheng Hou ,  Jung Wei Cheng ,  Yu-Min Liang ,  Tsung-Ding Wang

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/14

CPC classification number: H01L23/49816 ,  H01L24/73 ,  H01L24/32 ,  H01L24/16 ,  H01L25/0655 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/145 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/182 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16235 ,  H01L21/486

Abstract: Semiconductor device packages and methods of forming the same are discussed. In an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.

公开(公告)号：US20230307427A1

公开(公告)日：2023-09-28

申请号：US17806329

申请日：2022-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chi Lin ,  Hao-Cheng Hou ,  Tsung-Ding Wang ,  Chien-Hsun Lee ,  Shang-Yun Hou

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/24 ,  H01L25/18 ,  H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/16227 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/25174 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A method includes forming a build-up package substrate, which includes forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs, forming a first plurality of through-vias on the first plurality of RDLs, bonding an interconnect die to the second plurality of RDLs, encapsulating the interconnect die and the first plurality of through-vias in a first encapsulant, and forming a third plurality of RDLs over the first encapsulant. The third plurality of RDLs are electrically connected to the first plurality of through-vias. An organic package substrate is bonded to the build-up package substrate. The build-up package substrate and the organic package substrate in combination form a compound organic package substrate. A first package component and a second package component are bonded to the compound organic package substrate, and are electrically interconnected through the interconnect die.

公开(公告)号：US20220359436A1

公开(公告)日：2022-11-10

申请号：US17869080

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung Wei Cheng ,  Hai-Ming Chen ,  Chien-Hsun Lee ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Chun-Chih Chuang ,  Ming-Che Liu ,  Tsung-Ding Wang

IPC: H01L23/00 ,  H01L25/10 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/528

Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.

公开(公告)号：US11088069B2

公开(公告)日：2021-08-10

申请号：US16547583

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Chien-Hsun Lee ,  Chung-Shi Liu ,  Jung-Wei Cheng ,  Tsung-Ding Wang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a semiconductor die encapsulated by an insulating encapsulation, a redistribution circuit structure disposed over the semiconductor die and the insulating encapsulation, the redistribution circuit structure being electrically connected to the semiconductor die; and a conductive feature having a first portion embedded in the redistribution circuit structure and a second portion connected to the first portion, the first portion having a first long axis and a first short axis perpendicular to the long axis in a top view, the second portion disposed over and electrically connected to the first portion. A semiconductor device having the semiconductor package, a circuit substrate and a circuit board is also provided.

公开(公告)号：US20210242100A1

公开(公告)日：2021-08-05

申请号：US16869596

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Chien-Hsun Lee ,  Chung-Shi Liu ,  Jung-Wei Cheng ,  Tsung-Ding Wang ,  Yi-Yang Lei

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor package includes semiconductor dies, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The encapsulant encapsulates the semiconductor dies and is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the semiconductor dies. The high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer. The redistribution structure includes conductive patterns embedded in at least a pair of dielectric layers. The dielectric layers of the pair are made of a third material. The elastic modulus of the first material is higher than the elastic modulus of the third material. The elastic modulus of the second material is higher than the elastic modulus of the third material.

公开(公告)号：US20190123016A1

公开(公告)日：2019-04-25

申请号：US16221986

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jen Lin ,  Tsung-Ding Wang ,  Chien-Hsiun Lee ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0347 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/21 ,  H01L2224/27318 ,  H01L2224/27334 ,  H01L2224/27416 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/2076 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a bump structure disposed on a first substrate and a molding compound in physical contact with the bump structure. The bump structure protrudes from the molding compound. A conductive region is on a second substrate and contacts the bump structure. A no-flow underfill (NUF) material is vertically between the molding compound and the second substrate and laterally surrounds the bump structure. The NUF material is separated from the molding compound.

公开(公告)号：US09824902B1

公开(公告)日：2017-11-21

申请号：US15207512

申请日：2016-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Chien-Hsun Lee ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Jung-Wei Cheng ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Tsung-Ding Wang

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/3105 ,  H01L23/28

CPC classification number: H01L21/568 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68386 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/19102

Abstract: An integrated fan-out package including a chip module, a second integrated circuit, a second insulating encapsulation, and a redistribution circuit structure is provided. The chip module includes a first insulating encapsulation and a first integrated circuit embedded in the first insulating encapsulation, and the first integrated circuit includes a first surface and first conductive terminals on the first surface. The second integrated circuit includes a second surface and second conductive terminals on the second surface. The chip module and the second integrated circuit are embedded in the second insulating encapsulation. The first and second conductive terminals are accessibly exposed from the first and second insulating encapsulation. The redistribution circuit structure covers the first surface, the second surfaces, the first insulating encapsulation, and the second insulating encapsulation. The redistribution circuit structure is electrically connected to the first and second conductive terminals. Methods of fabricating the integrated fan-out package are also provided.

公开(公告)号：US20240047509A1

公开(公告)日：2024-02-08

申请号：US18150624

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Tsung-Ding Wang ,  Jung Wei Cheng ,  Chien-Hsun Lee ,  Shang-Yun Hou

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L25/10 ,  H01L27/01

CPC classification number: H01L28/10 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/49822 ,  H01L23/49833 ,  H01L21/565 ,  H01L25/105 ,  H01L27/01 ,  H01L23/5386 ,  H01L21/4853 ,  H01L23/5385 ,  H01L23/49838 ,  H01L21/486 ,  H01L23/5389 ,  H10B80/00

Abstract: A method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. The method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. The device die is electrically coupled to the inductor through the redistribution lines.

公开(公告)号：US11705378B2

公开(公告)日：2023-07-18

申请号：US16933910

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Wei Cheng ,  Jiun-Yi Wu ,  Hsin-Yu Pan ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/31 ,  H01L23/40 ,  H01L23/538

CPC classification number: H01L23/3135 ,  H01L23/4012 ,  H01L23/5383

Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

公开(公告)号：US20210125885A1

公开(公告)日：2021-04-29

申请号：US16666431

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Chien-Hsun Lee ,  Chung-Shi Liu ,  Hao-Cheng Hou ,  Hung-Jui Kuo ,  Jung-Wei Cheng ,  Tsung-Ding Wang ,  Yu-Hsiang Hu ,  Sih-Hao Liao

IPC: H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L23/16 ,  H01L21/56 ,  H01L25/00

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.