公开(公告)号：US09312218B2

公开(公告)日：2016-04-12

申请号：US13106591

申请日：2011-05-12

Applicant: DaeSik Choi ,  SooSan Park ,  HanGil Shin

Inventor： DaeSik Choi ,  SooSan Park ,  HanGil Shin

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die mounted to a substrate. A leadframe has a base plate and integrated tie bars and conductive bodies. The tie bars include a down step with an angled surface and horizontal surface between the conductive bodies. The leadframe is mounted to the semiconductor die and substrate with the base plate disposed on a back surface of the semiconductor die and the conductive bodies disposed around the semiconductor die and electrically connected to the substrate. An encapsulant is deposited over the substrate and semiconductor die and into the down step of the tie bars. A conductive layer is formed over the conductive bodies to inhibit oxidation. The leadframe is singulated through the encapsulant in the down step and through the horizontal portion of the tie bars to electrically isolate the conductive bodies. A semiconductor package can be mounted to the substrate and semiconductor die.

Abstract translation: 半导体器件具有安装到衬底的半导体管芯。 引线框架具有基板和集成的连接条和导电体。 连接杆包括在导电体之间具有成角度的表面和水平表面的向下的台阶。 引线框架安装到半导体管芯和衬底，其中基板设置在半导体管芯的背面上，导电体设置在半导体管芯周围并电连接到衬底。 密封剂沉积在衬底和半导体管芯上，并进入连接条的下降步骤。 导电体上形成导电层以抑制氧化。 引线框架在下降步骤中通过密封剂分离，并穿过连接条的水平部分，以电绝缘导电体。 半导体封装可以安装到衬底和半导体管芯。

公开(公告)号：US09305854B2

公开(公告)日：2016-04-05

申请号：US13795679

申请日：2013-03-12

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Jun Mo Koo

IPC: H01L23/48 ,  H01L23/28 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L23/532 ,  H01L23/538 ,  H01L23/525

CPC classification number: H01L23/28 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L23/5328 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench by disposing a stencil over the first insulating layer with an opening aligned with the patterned trench and depositing the conductive ink through the opening in the stencil into the patterned trench.Alternatively, the conductive ink is deposited by dispensing the conductive ink through a nozzle into the patterned trench. The conductive ink is cured by ultraviolet light at room temperature. A second insulating layer is formed over the first insulating layer and conductive ink. An interconnect structure is formed over the conductive ink. An encapsulant can be deposited around the semiconductor die. The patterned trench is formed in the encapsulant and the conductive ink is deposited in the patterned trench in the encapsulant.

Abstract translation: 半导体器件具有形成在半导体管芯上的半导体管芯和第一绝缘层。 图案化的沟槽形成在第一绝缘层中。 通过将第一绝缘层上的模版设置在与图案化的沟槽对准的开口并将导电油墨沉积在模板中的开口中，将导电油墨沉积在图案化的沟槽中，形成图案化沟槽。 或者，通过将导电油墨通过喷嘴分配到图案化的沟槽中来沉积导电油墨。 导电油墨在室温下通过紫外光固化。 在第一绝缘层和导电油墨之上形成第二绝缘层。 在导电油墨上形成互连结构。 密封剂可以沉积在半导体管芯周围。 图案化的沟槽形成在密封剂中，并且导电油墨沉积在密封剂中的图案化沟槽中。

公开(公告)号：US09299644B1

公开(公告)日：2016-03-29

申请号：US14285601

申请日：2014-05-22

Applicant: Byung Tai Do ,  Arnel Trasporto ,  Zigmund Ramirez Camacho

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Zigmund Ramirez Camacho

IPC: H01L23/495

CPC classification number: H01L23/49503 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.

Abstract translation: 一种集成电路封装系统的制造方法，包括：提供具有凹部的具有顶部的端子; 在所述凹陷中施加电介质材料，所述电介质材料在其中形成间隙并暴露所述顶部的一部分; 在所述间隙内形成迹线并与所述顶部直接接触，所述迹线在所述电介质材料的上表面上横向延伸; 并通过轨迹将集成电路连接到终端。

公开(公告)号：US20160071813A1

公开(公告)日：2016-03-10

申请号：US14935669

申请日：2015-11-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有轨迹线和集成凸块焊盘的衬底。 导电凸块材料沉积在衬底凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得凸块材料设置在管芯凸块焊盘和衬底凸块焊盘之间。 凸块材料在芯片凸块焊盘或基板凸块焊盘周围没有焊接掩模回流以形成互连。 凸块材料在管芯凸块焊盘或衬底凸块焊盘的占用面积内自我限制。 在回流之前，凸起材料可以浸入助熔剂溶液中以增加润湿性。 或者，互连包括不可熔基底和可熔盖。 选择凸起材料的体积，使得表面张力在回流期间保持凸块内的凸起材料的自我约束。

公开(公告)号：US09281259B2

公开(公告)日：2016-03-08

申请号：US14079273

申请日：2013-11-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jose Alvin Caparas ,  Glenn Omandam

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.

Abstract translation: 半导体器件具有安装到载体上的半导体管芯。 第一密封剂沉积在半导体管芯和载体上。 加强支撑构件可以设置在半导体管芯周围的载体上。 在第一密封剂中形成多个通道或凹槽。 可以通过去除第一密封剂的一部分来形成凹部。 或者，凹部形成在具有多个延伸表面的追逐模具中。 可以将第二密封剂沉积到第一密封剂的凹部中。 移除载体并且在半导体管芯和第一密封剂上形成互连结构。 第一密封剂的厚度提供足够的刚度以减少翘曲，同时凹槽在形成互连结构期间提供应力释放。 去除第一密封剂和凹部的一部分以减小半导体器件的厚度。

公开(公告)号：US09281228B2

公开(公告)日：2016-03-08

申请号：US13287035

申请日：2011-11-01

Applicant: DaeSik Choi ,  JoungIn Yang ,  MinJung Kim ,  Sang Mi Park ,  MinWook Yu

Inventor： DaeSik Choi ,  JoungIn Yang ,  MinJung Kim ,  Sang Mi Park ,  MinWook Yu

IPC: H01L21/00 ,  H01L21/683 ,  H01L23/36 ,  H01L23/42 ,  H01L29/06 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L23/36 ,  H01L23/42 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L29/0657 ,  H01L2221/68345 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/8485 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2924/0665 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/32057 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor die mounted to a substrate. A recess is formed in a back surface of the semiconductor die to an edge of the semiconductor die with sidewalls on at least two sides of the semiconductor die. The sidewalls are formed by removing a portion of the back surface of the die, or by forming a barrier layer on at least two sides of the die. A channel can be formed in the back surface of the semiconductor die to contain the TIM. A TIM is formed in the recess. A heat spreader is mounted in the recess over the TIM with a down leg portion of the heat spreader thermally connected to the substrate. The sidewalls contain the TIM to maintain uniform coverage of the TIM between the heat spreader and back surface of the semiconductor die.

Abstract translation: 半导体器件具有安装到衬底的半导体管芯。 在半导体管芯的后表面中形成有在半导体管芯的至少两侧具有侧壁的半导体管芯的边缘的凹部。 侧壁通过去除模具的后表面的一部分，或者通过在模具的至少两侧上形成阻挡层而形成。 可以在半导体管芯的后表面中形成通道以容纳TIM。 在凹部中形成有TIM。 散热器安装在TIM上的凹部中，散热器的下脚部分热连接到基板。 侧壁包含TIM以保持散热器和半导体管芯的后表面之间的TIM的均匀覆盖。

公开(公告)号：US09279673B2

公开(公告)日：2016-03-08

申请号：US13846593

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： WonJun Ko ,  SeungYong Chai ,  OhHan Kim ,  GwangTae Kim ,  Kenny Lee

IPC: G01K15/00 ,  G01N25/72 ,  G01N3/20 ,  G01B11/30 ,  H01L21/66

CPC classification number: G01B11/306 ,  H01L22/12

Abstract: A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.

Abstract translation: 翘曲测试系统使用校准块在温度曲线上校准翘曲测试系统。 校准块包括结合到第二金属块的第一金属块。 第一金属块包括第一金属和第二不同的金属。 第一金属块包括与第二金属块的CTE不同的CTE。 校准块设置在翘曲测试系统中。 在28℃至260℃的温度曲线上测量校准块的翘曲。记录校准块的测量翘曲与校准块在温度曲线上的已知热膨胀之间的偏差。 半导体封装中的翘曲测量通过校准块的测量翘曲与校准块在温度曲线上的已知热膨胀或翘曲之间的偏差来补偿。

公开(公告)号：US09269691B2

公开(公告)日：2016-02-23

申请号：US13918103

申请日：2013-06-14

Applicant: STATS ChipPAC, Ltd.

Inventor： HeeJo Chi ,  HanGil Shin ,  NamJu Cho

IPC: H01L23/49 ,  H01L23/00 ,  H01L23/36 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L21/683 ,  H01L23/522 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/24246 ,  H01L2224/24247 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/03 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor die. The semiconductor die is disposed over a conductive substrate. An encapsulant is deposited over the semiconductor die. A first interconnect structure is formed over the encapsulant. An opening is formed through the substrate to isolate a portion of the substrate electrically connected to the first interconnect structure. A bump is formed over the first interconnect structure. Conductive vias are formed through the encapsulant and electrically connected to the portion of the substrate. A plurality of bumps is formed over the semiconductor die. A first conductive layer is formed over the encapsulant. A first insulating layer is formed over the first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. Protrusions extend above the substrate.

Abstract translation: 半导体器件具有半导体管芯。 半导体管芯设置在导电衬底上。 密封剂沉积在半导体管芯上。 在密封剂上形成第一互连结构。 通过衬底形成开口以隔离电连接到第一互连结构的衬底的一部分。 在第一互连结构上形成凸块。 导电孔通过密封剂形成并电连接至基底的部分。 在半导体管芯上形成多个凸点。 在密封剂上形成第一导电层。 第一绝缘层形成在第一导电层上。 在第一绝缘层和第一导电层上形成第二导电层。 在第一绝缘层和第二导电层上形成第二绝缘层。 突起延伸到基底之上。

公开(公告)号：US09269595B2

公开(公告)日：2016-02-23

申请号：US13403859

申请日：2012-02-23

Applicant: HeeJo Chi ,  NamJu Cho ,  HanGil Shin

Inventor： HeeJo Chi ,  NamJu Cho ,  HanGil Shin

IPC: H01L21/44 ,  H01L21/50 ,  H01L21/78 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/50 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.

Abstract translation: 半导体晶片具有多个第一半导体管芯。 第二半导体管芯安装到第一半导体管芯。 第一半导体管芯的有源表面朝向第二半导体管芯的有源表面。 密封剂沉积在第一和第二半导体管芯上。 第二半导体管芯的与有源表面相对的后表面的一部分被去除。 在第二半导体管芯周围形成导电柱。 TSV可以通过第一半导体管芯形成。 在第二半导体管芯，密封剂和导电柱的后表面上形成互连结构。 互连结构电连接到导电柱。 去除与活性表面相对的第一半导体管芯的后表面的一部分。 可以在第一半导体管芯的后表面上形成散热器或屏蔽层。

公开(公告)号：US20160043047A1

公开(公告)日：2016-02-11

申请号：US14814906

申请日：2015-07-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Sze Ping Goh ,  Jose A. Caparas

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/24155 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

Abstract translation: 半导体器件包括包括导电层的第一半导体封装。 包括互连结构的衬底设置在导电层上。 具有第一半导体封装的导电层的衬底的互连结构是自对准的。 在基板上形成多个开口。 粘合剂设置在基板和第一半导体封装之间以及基板的开口中。 在与衬底相对的第一半导体封装件上方形成再分配层（RDL）。 衬底的间距与RDL的间距不同。 粘合剂延伸到基底的互连结构。 第二半导体封装设置在衬底和第一半导体封装之上。