公开(公告)号：US06653170B1

公开(公告)日：2003-11-25

申请号：US09777533

申请日：2001-02-06

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4554 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01202 ,  H01L2924/01203 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48

Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The chip includes a conductive pad and the support circuit includes a conductive trace. An elongated wire that electrically connects the pad to the trace is attached to the pad by a wire bond and attached to the trace by a plated connection joint. Preferably, an electrically conductive path between and in contact with the pad and the trace includes the elongated wire and excludes solder and conductive adhesive. A method of manufacturing the assembly includes forming the wire bond using thermocompression or thermosonic ball bonding and then forming the connection joint using electroless plating.

Abstract translation: 半导体芯片组件包括附接到支撑电路的半导体芯片。 芯片包括导电焊盘，支撑电路包括导电迹线。 将焊盘与迹线电连接的细长导线通过引线接合附接到焊盘，并通过电镀连接接头附接到迹线。 优选地，在焊盘和迹线之间和之间的导电路径包括细长线，并且不包括焊料和导电粘合剂。 制造该组件的方法包括使用热压或热球球接合形成线接合，然后使用无电镀形成连接接头。

公开(公告)号：US06444489B1

公开(公告)日：2002-09-03

申请号：US09738667

申请日：2000-12-15

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/32134 ,  H01L21/76894 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/78301 ,  H01L2224/82039 ,  H01L2224/92144 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor chip assembly includes a semiconductor chip and a molded substrate. The chip includes a conductive pad. The molded substrate includes a base, a bump that extends above the base, and a through-hole in the base that is offset from the bump and aligned with the pad. A routing line covers the bump and extends along a top surface of the molded substrate to the through-hole and extends through the through-hole and contacts the pad. The molded substrate is compressible and permits a portion of the routing line that covers the bump to exhibit elastic deformation in response to vertically oriented external pressure. A method of manufacturing the assembly includes forming the molded substrate and attaching the molded substrate to the chip by transfer molding, exposing the pad using the through-hole, depositing a metal layer on the molded substrate and in the through-hole and on the pad, and removing a portion of the metal layer to form the routing line.

Abstract translation: 半导体芯片组件包括半导体芯片和模制基板。 芯片包括导电垫。 模制基底包括基部，在基部之上延伸的凸起，以及在基部中的从凸块偏移并与衬垫对准的通孔。 布线线覆盖凸块并且沿着模制基底的顶表面延伸到通孔并延伸穿过通孔并接触垫。 模制的基底是可压缩的并且允许覆盖凸起的路线的一部分响应于垂直取向的外部压力而呈现弹性变形。 一种制造该组件的方法包括：形成模制基片并通过传递模塑将模制基底附着到芯片上，使用通孔露出垫，在模制基底上以及通孔和垫上沉积金属层 并且去除金属层的一部分以形成布线线。

公开(公告)号：US06440835B1

公开(公告)日：2002-08-27

申请号：US09687619

申请日：2000-10-13

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L24/11 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/78301 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2224/48 ,  H01L2924/20752 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05624

Abstract: A method of connecting a conductive trace to a semiconductor chip includes aligning a conductive pad on the chip with a through-hole in the conductive trace while a base covers the through-hole on a side opposite the chip wherein the conductive trace and the base are different materials, removing some or all of the base thereby exposing the through-hole, and forming a connection joint in the through-hole that electrically connects the conductive trace and the pad. The method may include electroplating the conductive trace onto the base, mechanically attaching the chip to the conductive trace using an adhesive after aligning the pad and the through-hole and before removing some or all of the base, and forming an opening in the adhesive directly beneath the through-hole thereby exposing the pad after removing some or all of the base and before forming the connection joint.

Abstract translation: 将导电迹线连接到半导体芯片的方法包括将芯片上的导电焊盘与导电迹线中的通孔对准，同时基底覆盖与芯片相对的一侧上的通孔，其中导电迹线和基极为 不同的材料，去除部分或全部的基底，从而露出通孔，并在通孔中形成连接导电迹线和焊盘的连接接头。 该方法可以包括将导电迹线电镀到基底上，在将衬垫和通孔对准之后并且在去除部分或全部基底之前使用粘合剂将芯片机械地附接到导电迹线，并且直接在粘合剂中形成开口 在通孔下面，从而在去除部分或全部基座之后并在形成连接接头之前露出垫。

公开(公告)号：US06403460B1

公开(公告)日：2002-06-11

申请号：US09878522

申请日：2001-06-11

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L21/2885 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor chip assembly includes providing a semiconductor chip that includes a conductive pad, and providing a support circuit that includes an insulative base and a conductive trace. One embodiment includes mechanically attaching the chip to the support circuit using an adhesive such that a portion of the pad is directly beneath the conductive trace, and then applying an etch to form openings in the base and the adhesive such that the opening in the base exposes the conductive trace and the openings expose the pad. Another embodiment includes disposing an adhesive beneath the support circuit, applying an etch to form openings in the base and the adhesive, and then mechanically attaching the chip to the support circuit using the adhesive such that the opening in the base exposes the conductive trace and the openings expose the pad. Preferably, a connection joint is formed inside the openings that contacts and electrically connects the conductive trace and the pad.

Abstract translation: 制造半导体芯片组件的方法包括提供包括导电焊盘的半导体芯片，以及提供包括绝缘基底和导电迹线的支撑电路。 一个实施例包括使用粘合剂将芯片机械地附接到支撑电路，使得焊盘的一部分直接在导电迹线下方，然后施加蚀刻以在基部和粘合剂中形成开口，使得基体中的开口暴露 导电迹线和开口露出垫。 另一个实施例包括在支撑电路下方设置粘合剂，施加蚀刻以在基底和粘合剂中形成开口，然后使用粘合剂将芯片机械地附接到支撑电路，使得基体中的开口暴露导电迹线和 开口露出垫。 优选地，在开口内形成接触和电连接导电迹线和焊盘的连接接头。

公开(公告)号：US5358604A

公开(公告)日：1994-10-25

申请号：US953520

申请日：1992-09-29

Applicant: Charles W. C. Lin ,  Chung J. Lee ,  Tom J. Hirsch ,  Kimcuc T. Tran

Inventor： Charles W. C. Lin ,  Chung J. Lee ,  Tom J. Hirsch ,  Kimcuc T. Tran

IPC: C25D5/02 ,  G03F7/00 ,  H05K3/02 ,  H05K3/20 ,  B05D1/00

CPC classification number: B29C43/003 ,  B82Y10/00 ,  B82Y40/00 ,  C23C16/01 ,  C23C16/04 ,  C23C16/06 ,  C25D5/022 ,  G03F7/0002 ,  H05K3/20 ,  H05K3/205 ,  B29C2043/025 ,  H05K2203/0113 ,  H05K2203/0117 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/1338 ,  H05K3/027

Abstract: The invention provides an apparatus and methods of using the apparatus to transfer conductive patterns onto substrates under conditions of heat and pressure. The apparatus comprises a master mold with a printing surface on which is produced a permanent mirror image of the conductive pattern to be created. This pattern is then coated with a loosely adherent film of conductive metal, such as copper, which is transferred onto a substrate to be printed.

Abstract translation: 本发明提供一种使用该装置在热和压力条件下将导电图案转印到基板上的装置和方法。 该设备包括具有印刷表面的母模，其上产生将要产生的导电图案的永久镜像。 然后将该图案涂覆有导电金属（例如铜）的松散粘附的膜，其被转印到待印刷的基底上。

公开(公告)号：US5192581A

公开(公告)日：1993-03-09

申请号：US822383

申请日：1992-01-14

Applicant: Tom J. Hirsch ,  Charles W. C. Lin ,  Chung J. Lee ,  Heinrich G. O. Muller

Inventor： Tom J. Hirsch ,  Charles W. C. Lin ,  Chung J. Lee ,  Heinrich G. O. Muller

IPC: C23C18/16 ,  H05K3/18 ,  B05D3/06 ,  B05D5/12 ,  H01L21/306

CPC classification number: H05K3/185 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/204 ,  C23C18/2066 ,  C23C18/30 ,  C23C18/32 ,  C23C18/38 ,  C23C18/42 ,  H05K2203/107

Abstract: A dielectric substrate is coated with a protective layer and a catalyst film is formed in a laser irradiated predetermined pattern on the protective layer so that during electroless deposition a metal is plated on the catalyst film in the predetermined pattern whether or not the dielectric has unwanted catalytic sites. The protective layer is not removed by the electroless plating bath or prior etch steps but can subsequently be stripped by a separate etch without removing the plated metal or the dielectric from the substrate.

Abstract translation: 电介质基板被涂覆有保护层，并且在保护层上以激光照射的预定图案形成催化剂膜，使得在无电沉积期间，以预定图案将金属镀在催化剂膜上，无论电介质是否有不希望的催化 网站。 保护层不通过化学镀浴或先前的蚀刻步骤去除，但是随后可以通过单独的蚀刻来剥离保护层，而不从衬底去除镀覆的金属或电介质。

公开(公告)号：US08865525B2

公开(公告)日：2014-10-21

申请号：US13532941

申请日：2012-06-26

Applicant: Charles W. C. Lin ,  Chia Chung Wang

Inventor： Charles W. C. Lin ,  Chia Chung Wang

IPC: H05K1/11 ,  H05K3/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/10 ,  H01L21/683 ,  H01L23/367 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/24101 ,  H01L2224/24221 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/82106 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/3511 ,  Y10T29/49124 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A method of making a cavity substrate. The method includes: preparing a supporting board including a stiffener, a bump/flange sacrificial carrier, an adhesive and an electrical pad, wherein the adhesive bonds the stiffener to the sacrificial carrier; forming a careless build-up circuitry on the supporting board in contact with the bump and the stiffener; and removing the bump to form a cavity and expose the electrical pad from a closed end of the cavity; wherein the cavity is laterally covered and surrounded by the adhesive. A semiconductor device can be mounted on the cavity substrate and electrically connected to the electrical pad. The careless buildup circuitry provide signal routing for the semiconductor device while the built-in stiffener can provide adequate mechanical support for the careless build-up circuitry and the semiconductor device.

Abstract translation: 一种制造空腔衬底的方法。 该方法包括：制备包括加强件，凸块/凸缘牺牲载体，粘合剂和电垫的支撑板，其中粘合剂将加强件粘合到牺牲载体上; 在与所述凸起和所述加强件接触的所述支撑板上形成粗心的积聚电路; 并且去除所述凸起以形成空腔并使所述电垫从所述空腔的封闭端露出; 其中腔被横向覆盖并被粘合剂包围。 半导体器件可以安装在空腔衬底上并电连接到电焊盘。 不小心积累电路为半导体器件提供信号路由，而内置的加强件可以为不小心的积聚电路和半导体器件提供足够的机械支持。

公开(公告)号：US08415703B2

公开(公告)日：2013-04-09

申请号：US12876106

申请日：2010-09-04

Applicant: Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

Inventor： Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

IPC: H01L33/00

CPC classification number: H01L21/486 ,  H01L23/3677 ,  H01L33/486 ,  H01L33/642 ,  H01L2224/73265 ,  H01L2924/15153 ,  H01L2933/0075 ,  H05K1/0204 ,  H05K3/0061 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2203/0369

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post, a base and a flange. The conductive trace includes a pad and a terminal. The semiconductor device extends into a cavity in the flange, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, the flange extends upwardly from the post in the opening and extends laterally above the adhesive, the cavity extends into the opening and the base extends laterally from the post. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线和粘合剂。 散热器包括柱，基座和凸缘。 导电迹线包括焊盘和端子。 半导体器件延伸到法兰中的空腔中，电连接到导电迹线并与散热器热连接。 柱从基部向上延伸到粘合剂中的开口中，凸缘从开口中的柱向上延伸并且在粘合剂的上方横向延伸，空腔延伸到开口中，并且基部从柱横向延伸。 导电迹线位于腔体外部，并在焊盘和端子之间提供信号路由。

公开(公告)号：US08354688B2

公开(公告)日：2013-01-15

申请号：US13337054

申请日：2011-12-24

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L33/00

CPC classification number: H05K1/021 ,  H01L21/486 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4084 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/10106 ,  H05K2203/049 ,  H05K2203/063 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线和双重粘合剂。 散热器包括凸块，底座和凸缘。 导电迹线包括焊盘和端子。 半导体器件安装在凸块中的凸起中的凸起中，电连接到导电迹线并且热连接到散热器。 凸块延伸到第一粘合剂中的开口中并且与第二粘合剂中的开口对准并与之隔开。 底座和凸缘从凸块横向延伸。 第一粘合剂被夹在基部和凸缘之间，第二粘合剂夹在导电迹线和凸缘之间，并且凸缘夹在粘合剂之间。 导电迹线位于腔体外部，并在焊盘和端子之间提供信号路由。

公开(公告)号：US08354283B2

公开(公告)日：2013-01-15

申请号：US13337164

申请日：2011-12-26

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L21/00

CPC classification number: H05K1/021 ,  H01L21/486 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4084 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/10106 ,  H05K2203/049 ,  H05K2203/063 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of making a semiconductor chip assembly includes providing a bump and a ledge, mounting a first adhesive on the ledge including inserting the bump into an opening in the first adhesive, mounting a conductive layer on the first adhesive including aligning the bump with an aperture in the conductive layer, then flowing the first adhesive between the bump and the conductive layer, solidifying the first adhesive, then providing a heat spreader that includes the bump, a base and the ledge, then mounting a second adhesive on the ledge, mounting a conductive trace that includes a pad and a terminal on the second adhesive, then mounting a semiconductor device on the bump in a cavity in the bump, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract translation: 制造半导体芯片组件的方法包括提供凸块和凸缘，将第一粘合剂安装在凸缘上，包括将凸块插入第一粘合剂中的开口中，将导电层安装在第一粘合剂上，包括使凸块与孔 在导电层中，然后使第一粘合剂在凸起和导电层之间流动，固化第一粘合剂，然后提供包括凸块，底座和凸缘的散热器，然后将第二粘合剂安装在凸缘上， 导电迹线，其包括第二粘合剂上的焊盘和端子，然后将凸块中的半导体器件安装在凸块中的空腔中，将半导体器件电连接到导电迹线并将半导体器件热连接到散热器。