公开(公告)号：US08236687B2

公开(公告)日：2012-08-07

申请号：US12854278

申请日：2010-08-11

Applicant: Hsiu-Jen Lin ,  Jian-Shian Lin ,  Shau-Yi Chen ,  Chieh-Lung Lai

Inventor： Hsiu-Jen Lin ,  Jian-Shian Lin ,  Shau-Yi Chen ,  Chieh-Lung Lai

IPC: H01L21/44

CPC classification number: H01L23/53247 ,  H01L24/29 ,  H01L24/83 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/30 ,  H01L33/40 ,  H01L33/486 ,  H01L33/62 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/83193 ,  H01L2224/83207 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83948 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2933/0066 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid -solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time for performing a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C.

Abstract translation: 芯片接合方法适合于将具有第一金属薄膜层的LED芯片芯片接合到基板上。 该方法包括在基板的表面上形成第二金属薄膜层; 在所述第二金属薄膜层上形成芯片接合材料层; 将第一金属薄膜层与芯片接合材料层接触，将LED芯片放置在芯片接合材料层上; 在液固固化反应温度下加热芯片接合材料层达预固化时间，以形成第一金属间层和第二金属间层; 并在固 - 固反应温度下加热芯片接合材料层进行固 - 固反应的固化时间。 液固反应温度和固 - 固反应温度均低于110℃，固 - 固反应后第一和第二金属间化合物的熔点高于200℃。

公开(公告)号：US09768137B2

公开(公告)日：2017-09-19

申请号：US13460412

申请日：2012-04-30

Applicant: Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/367

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/3677 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/1134 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.

公开(公告)号：US09607921B2

公开(公告)日：2017-03-28

申请号：US13349405

申请日：2012-01-12

Applicant: Wen-Hsiung Lu ,  Yi-Wen Wu ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Wen-Hsiung Lu ,  Yi-Wen Wu ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3192 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/03823 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/10126 ,  H01L2224/11464 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/73104 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.

公开(公告)号：US09538582B2

公开(公告)日：2017-01-03

申请号：US13559318

申请日：2012-07-26

Applicant: Ming-Da Cheng ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Wei-Yu Chen ,  Chien-Wei Lee ,  Chung-Shi Liu

Inventor： Ming-Da Cheng ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Wei-Yu Chen ,  Chien-Wei Lee ,  Chung-Shi Liu

IPC: B23K31/02 ,  H01L21/00 ,  H05B3/02 ,  H01L21/677 ,  H01L21/683 ,  H01L23/00

CPC classification number: H05B3/02 ,  B23K3/087 ,  B23K2101/40 ,  H01L21/67721 ,  H01L21/6838 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/75744 ,  H01L2224/7598 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/3511 ,  H01L2924/37001 ,  Y10T29/41 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

Abstract translation: 一种方法包括将第一包装部件放置在真空舟皿上，其中真空舟皿包括孔，并且其中第一包装部件覆盖该孔。 第二包装部件放置在第一包装部件上，其中焊料区域设置在第一和第二包装部件之间。 该孔被抽真空，其中第一包装部件被压靠在真空舟皿上的压力，并且其中压力由孔中的真空产生。 当保持孔中的真空时，回流焊接区域以将第二包装部件结合到第一包装部件。

公开(公告)号：US08927391B2

公开(公告)日：2015-01-06

申请号：US13118108

申请日：2011-05-27

Applicant: Meng-Tse Chen ,  Wei-Hung Lin ,  Sheng-Yu Wu ,  Chun-Cheng Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Chih-Wei Lin ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Wei-Hung Lin ,  Sheng-Yu Wu ,  Chun-Cheng Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Chih-Wei Lin ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/30 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16055 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/00

Abstract: A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film.

Abstract translation: 包装方法包括将包装部件放置在脱模膜上，其中包装部件表面上的焊球与剥离膜物理接触。 接下来，填充在剥离膜和包装部件之间的模塑料固化，其中在固化步骤期间，焊球与剥离膜保持物理接触。

公开(公告)号：US08735273B2

公开(公告)日：2014-05-27

申请号：US13179299

申请日：2011-07-08

Applicant: Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Yi-Wen Wu ,  Hsiu-Jen Lin ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Yi-Wen Wu ,  Hsiu-Jen Lin ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L21/44

CPC classification number: H01L24/03 ,  H01L21/566 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

Abstract translation: 一种方法包括在覆盖半导体衬底的金属焊盘上形成钝化层。 在钝化层中形成第一开口，金属垫的一部分通过第一开口暴露。 种子层形成在钝化层之上并且电耦合到金属焊盘。 种子层还包括钝化层上的部分。 在种子层上形成第一掩模，其中第一掩模具有直接在金属焊盘的至少一部分上的第二开口。 在种子层和第二开口中形成PPI。 在第一掩模上形成第二掩模，第二掩模形成在第二掩模中。 金属凸块的一部分形成在第三开口中。 在形成金属凸块的部分的步骤之后，去除第一和第二掩模。

公开(公告)号：US08674496B2

公开(公告)日：2014-03-18

申请号：US13399437

申请日：2012-02-17

Applicant: Cheng-Chung Lin ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Cheng-Chung Lin ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/07

CPC classification number: H01L24/14 ,  H01L23/49816 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract translation: 提供了一种精细节距封装（PoP）和一种形成方法。 PoP可以通过将连接例如焊球放置在具有附接到其上的半导体管芯的第一基板上而形成。 执行第一回流处理以延长焊球。 此后，具有安装有另一个半导体管芯的第二基板连接到焊球。 执行第二回流处理以形成沙漏连接。

公开(公告)号：US20130214401A1

公开(公告)日：2013-08-22

申请号：US13399437

申请日：2012-02-17

Applicant: Cheng-Chung Lin ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Cheng-Chung Lin ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/07 ,  H01L21/50

CPC classification number: H01L24/14 ,  H01L23/49816 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract translation: 提供了一种精细节距封装（PoP）和一种形成方法。 PoP可以通过将连接例如焊球放置在具有附接到其上的半导体管芯的第一基板上而形成。 执行第一回流处理以延长焊球。 此后，具有安装有另一个半导体管芯的第二基板连接到焊球。 执行第二回流处理以形成沙漏连接。

公开(公告)号：US08501615B2

公开(公告)日：2013-08-06

申请号：US13161303

申请日：2011-06-15

Applicant: Ming-Da Cheng ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Tzong-Hann Yang ,  Wen-Hsiung Lu ,  Zheng-Yi Lim ,  Yi-Wen Wu ,  Chung-Shi Liu

Inventor： Ming-Da Cheng ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Tzong-Hann Yang ,  Wen-Hsiung Lu ,  Zheng-Yi Lim ,  Yi-Wen Wu ,  Chung-Shi Liu

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L21/6836 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/1133 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/11

Abstract: A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

Abstract translation: 提供一种用于形成金属凸块的系统和方法。 一个实施例包括将导电材料附着到载体介质上，然后将导电材料接触到基底的导电区域。 然后使用接合工艺将导电材料的部分结合到导电区域，以在导电区域上形成导电盖，并且去除残留的导电材料和载体介质。 回流工艺用于将导电盖重新流到导电凸块中。

公开(公告)号：US20130009307A1

公开(公告)日：2013-01-10

申请号：US13179299

申请日：2011-07-08

Applicant: Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Yi-Wen Wu ,  Hsiu-Jen Lin ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Yi-Wen Wu ,  Hsiu-Jen Lin ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L24/03 ,  H01L21/566 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

Abstract translation: 一种方法包括在覆盖在半导体衬底上的金属焊盘上形成钝化层。 在钝化层中形成第一开口，金属垫的一部分通过第一开口暴露。 种子层形成在钝化层之上并且电耦合到金属焊盘。 种子层还包括钝化层上的部分。 在种子层上形成第一掩模，其中第一掩模具有直接在金属焊盘的至少一部分上的第二开口。 在种子层和第二开口中形成PPI。 在第一掩模上形成第二掩模，第二掩模形成在第二掩模中。 金属凸块的一部分形成在第三开口中。 在形成金属凸块的部分的步骤之后，去除第一和第二掩模。