公开(公告)号：US09627253B2

公开(公告)日：2017-04-18

申请号：US15142885

申请日：2016-04-29

申请人： SK hynix Inc.

发明人： Min-Ho Kim

IPC分类号： H01L21/768 ,  H01L21/764 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L27/108 ,  H01L27/24 ,  H01L23/532 ,  H01L23/528 ,  H01L23/535 ,  H01L29/423 ,  H01L23/48

CPC分类号： H01L21/7682 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/2436 ,  H01L29/4236 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure.

公开(公告)号：US09564444B2

公开(公告)日：2017-02-07

申请号：US14874392

申请日：2015-10-03

申请人： International Business Machines Corporation

发明人： Kevin K. Chan ,  Babar A. Khan ,  Dae-Gyu Park ,  Xinhui Wang

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L29/66 ,  H01L27/12 ,  H01L49/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10861 ,  H01L27/10879 ,  H01L27/1211 ,  H01L28/40 ,  H01L29/04 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/66181 ,  H01L29/66795 ,  H01L29/945

摘要： At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.

摘要翻译： 在绝缘体上半导体（SOI）衬底上形成至少一个介质衬垫层。 在SOI衬底中形成深沟槽，并且外部电极，节点电介质和内部电极的组合形成为使得内部电极的顶表面凹入到埋入式绝缘体层的顶表面之下 SOI衬底。 执行选择性外延以用外延半导体材料部分填充覆盖内部电极的空腔。 将顶部半导体材料层和外延半导体材料部分图案化以形成包括顶部半导体材料层的一部分和外延半导体材料部分的一部分的鳍状结构。 外延半导体材料部分在内部电极和形成在鳍状结构上的半导体器件之间用作导电带结构。

公开(公告)号：US09564217B1

公开(公告)日：2017-02-07

申请号：US14886116

申请日：2015-10-19

申请人： UNITED MICROELECTRONICS CORP.

发明人： Zhibiao Zhou ,  Chen-Bin Lin ,  Chi-Fa Ku ,  Shao-Hui Wu

IPC分类号： H01L27/10 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  G11C14/00 ,  H01L29/786 ,  H01L27/108 ,  H01L27/105

CPC分类号： G11C14/0009 ,  G11C14/0027 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/60

摘要： A semiconductor memory device includes a semiconductor substrate having a main surface, at least a first dielectric layer on the main surface of the semiconductor substrate, a first OS FET device and a second OS FET device disposed on the first dielectric layer, at least a second dielectric layer covering the first dielectric layer, the first OS FET device, and the second OS FET device, a first MIM capacitor on the second dielectric layer and electrically coupled to the first OS FET device, and a second MIM capacitor on the second dielectric layer and electrically coupled to the second OS FET device.

摘要翻译： 半导体存储器件包括具有主表面的半导体衬底，在半导体衬底的主表面上的至少第一电介质层，设置在第一介电层上的第一OS FET器件和第二OS FET器件，至少第二 覆盖第一电介质层的介质层，第一OS FET器件和第二OS FET器件，第二介电层上的第一MIM电容器，并且电耦合到第一OS FET器件;以及第二MIM电容器， 并电耦合到第二OS FET器件。

公开(公告)号：US09540728B2

公开(公告)日：2017-01-10

申请号：US15190578

申请日：2016-06-23

申请人： HITACHI KOKUSAI ELECTRIC INC.

发明人： Atsushi Moriya ,  Naoharu Nakaiso ,  Yugo Orihashi ,  Kotaro Murakami

IPC分类号： C23C16/00 ,  C23C16/455 ,  H01L27/108 ,  H01L21/02 ,  H01L27/115 ,  C23C16/24

CPC分类号： H01L21/02609 ,  C23C16/0272 ,  C23C16/24 ,  C23C16/4408 ,  C23C16/45523 ,  C23C16/45529 ,  C23C16/45544 ,  C23C16/46 ,  C23C16/52 ,  C23C16/56 ,  C30B25/04 ,  C30B25/165 ,  C30B25/186 ,  C30B25/20 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/02694 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/67103 ,  H01L21/67115 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10891 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

摘要： A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.

摘要翻译： 制造半导体器件的方法包括交替地向含有单晶硅和绝缘膜暴露的表面的衬底提供含有硅和卤素元素的第一工艺气体，并提供含有硅并且不含卤素的第二工艺气体 元件，并且向衬底提供含有硅的第三工艺气体，由此第一硅膜在单晶硅上同构外延生长，并且在绝缘体上生长晶体结构与第一硅膜不同的第二硅膜 电影。

公开(公告)号：US20160314981A1

公开(公告)日：2016-10-27

申请号：US15084479

申请日：2016-03-30

申请人： Samsung Electronics Co., Ltd.

发明人： Junho YOON ,  KyungYub JEON ,  Kyohyeok KIM ,  Jaehong PARK ,  Je-Woo HAN

IPC分类号： H01L21/3065 ,  H01L21/02 ,  H01L21/308

CPC分类号： H01L21/3081 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/28044 ,  H01L21/28123 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1085

摘要： A method for forming a vertical pattern includes forming a tungsten layer on a lower layer and performing a cyclic process including an etch process and an oxidation process on the tungsten layer to form a vertical pattern. Performing the cyclic process includes oxidizing the tungsten layer by an oxidation process using oxygen plasma to form a tungsten oxide layer and selectively etching the tungsten oxide layer by an etch process using a chlorine-based gas.

摘要翻译： 用于形成垂直图案的方法包括在下层上形成钨层，并在钨层上执行包括蚀刻工艺和氧化工艺的循环过程以形成垂直图案。 执行循环过程包括通过使用氧等离子体的氧化工艺氧化钨层以形成氧化钨层，并通过使用氯基气体的蚀刻工艺选择性地蚀刻氧化钨层。

公开(公告)号：US20160307905A1

公开(公告)日：2016-10-20

申请号：US15130675

申请日：2016-04-15

申请人： L'Air Liquide, Société Anonyme pour I'Etude et I'Exploitation des Procédés Georges Claude

发明人： Clément LANSALOT-MATRAS ,  Wontae NOH

IPC分类号： H01L27/108 ,  H01L49/02 ,  C07F9/00 ,  H01L21/285

CPC分类号： H01L27/1085 ,  C23C16/18 ,  C23C16/32 ,  C23C16/34 ,  C23C16/405 ,  C23C16/42 ,  C23C16/45525 ,  C23C16/45553 ,  C23C16/50 ,  H01G4/10 ,  H01G4/20 ,  H01G13/003 ,  H01L21/28556 ,  H01L21/28568 ,  H01L27/10805 ,  H01L28/60

摘要： Vanadium-containing film forming compositions are disclosed, along with methods of synthesizing the same, and methods of forming Vanadium-containing films on one or more substrates via vapor deposition processes using the Vanadium-containing film forming compositions.

摘要翻译： 公开了含钒成膜组合物及其合成方法，以及通过使用含钒成膜组合物的气相沉积工艺在一个或多个基材上形成含钒膜的方法。

公开(公告)号：US20160300613A1

公开(公告)日：2016-10-13

申请号：US15191137

申请日：2016-06-23

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  G11C11/407 ,  H01L27/108 ,  H01L29/78

CPC分类号： G11C14/0045 ,  G11C11/21 ,  G11C11/404 ,  G11C11/407 ,  G11C11/4072 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0027 ,  G11C14/0036 ,  G11C14/009 ,  G11C2013/0073 ,  H01L27/10802 ,  H01L27/1085 ,  H01L27/10879 ,  H01L27/2436 ,  H01L29/7841 ,  H01L45/00 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

公开(公告)号：US09460964B2

公开(公告)日：2016-10-04

申请号：US15013389

申请日：2016-02-02

申请人： SK hynix Inc.

发明人： Hyung-Kyun Kim

IPC分类号： H01L21/32 ,  H01L21/47 ,  H01L21/768 ,  H01L27/108 ,  H01L21/28 ,  H01L21/311 ,  H01L21/324 ,  H01L27/22 ,  H01L27/24

CPC分类号： H01L21/76897 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76883 ,  H01L27/1085 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/228 ,  H01L27/2436

摘要： A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate. A sacrificial spacer is formed on sidewalls of the insulating layer defining the contact hole. A polysilicon layer pattern is formed in the contact hole. The sacrificial spacer is removed to form an air gap around the polysilicon layer pattern. A thermal process is performed to remove a seam existing in the polysilicon layer pattern.

公开(公告)号：US20160284710A1

公开(公告)日：2016-09-29

申请号：US15179809

申请日：2016-06-10

申请人： SK hynix Inc.

发明人： You-Song KIM ,  Jin-Ki JUNG

IPC分类号： H01L27/108 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/764

CPC分类号： H01L27/10885 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/764 ,  H01L27/1085 ,  H01L27/10891

摘要： A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.

公开(公告)号：US09449964B2

公开(公告)日：2016-09-20

申请号：US14730230

申请日：2015-06-03

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC分类号： H01L21/768 ,  H01L27/06 ,  H01L21/28 ,  H01L27/108 ,  H01L49/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/40

CPC分类号： H01L27/0629 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1085 ,  H01L28/60 ,  H01L28/75 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66545

摘要： A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

摘要翻译： 半导体结构包括金属栅极，第二电介质层和接触插塞。 金属栅极位于基板和第一电介质层中，其中金属栅极包括具有U形横截面轮廓的功函数金属层和位于功函数金属层上的低电阻率材料。 第二电介质层位于金属栅极和第一电介质层上。 接触塞位于第二电介质层上，在第三电介质层中形成电容器。 此外，本发明还提供了形成所述半导体结构的半导体工艺。