公开(公告)号：US20130277841A1

公开(公告)日：2013-10-24

申请号：US13452589

申请日：2012-04-20

申请人： Mirng-Ji Lii ,  Chen-Hua Yu ,  Chien-Hsiun Lee ,  Yung Ching Chen ,  Jiun Yi Wu

发明人： Mirng-Ji Lii ,  Chen-Hua Yu ,  Chien-Hsiun Lee ,  Yung Ching Chen ,  Jiun Yi Wu

IPC分类号： H01L25/07 ,  H01L21/60

CPC分类号： H01L23/49838 ,  H01L23/49811 ,  H01L23/5283 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00

摘要： System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling and may have an anti-oxidation coating. The interconnect may be attached to mounting pads on the top and bottom packages via an electrically conductive adhesive, including, but not limited to solder and solder paste. A solder preservative or other anti-oxidation coating may be applied to the mounting pad. A package-on-package assembly with solid interconnects may have a top package configured to accept at least one electronic device, with the solid interconnects mounted between the top package and a bottom package to rigidly hold the package about parallel to each other.

摘要翻译： 公开了用于在两个基板安装的封装之间创建刚性互连以产生封装封装组件的系统和方法。 固体互连可以具有预定长度，其被配置为提供预定的包装分离，可以是圆柱形，圆锥形或阶梯形，可以通过挤出，浇铸，拉拔或研磨形成，并且可以具有抗氧化涂层。 互连可以经由导电粘合剂附接到顶部和底部封装上的安装焊盘，包括但不限于焊料和焊膏。 可以将焊料防腐剂或其它抗氧化涂层施加到安装垫。 具有固体互连的封装封装组件可以具有被配置为接纳至少一个电子器件的顶部封装，其中固体互连件安装在顶部封装和底部封装之间，以使封装彼此平行地刚性地保持。

公开(公告)号：US20130270693A1

公开(公告)日：2013-10-17

申请号：US13445699

申请日：2012-04-12

申请人： Yu-Jen Tseng ,  Guan-Yu Chen ,  Sheng-Yu Wu ,  Chen-Hua Yu ,  Mirng-Ji Lii ,  Chen-Shien Chen ,  Tin-Hao Kuo

发明人： Yu-Jen Tseng ,  Guan-Yu Chen ,  Sheng-Yu Wu ,  Chen-Hua Yu ,  Mirng-Ji Lii ,  Chen-Shien Chen ,  Tin-Hao Kuo

IPC分类号： H01L23/498 ,  G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2224/1144

摘要： A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.

摘要翻译： 一种用于防止在跟踪轨迹结构中的相邻金属迹线桥接的方法和装置。 一个实施例包括确定包装部件的热膨胀系数（CTE）和工艺参数。 然后分析设计参数，并且可以基于包装部件的CTE和工艺参数来修改设计参数。

公开(公告)号：US08558229B2

公开(公告)日：2013-10-15

申请号：US13313747

申请日：2011-12-07

申请人： Shin-Puu Jeng ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Chen-Hua Yu ,  Tzuan-Horng Liu ,  Tzu-Wei Chiu ,  Kuo-Ching Hsu

发明人： Shin-Puu Jeng ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Chen-Hua Yu ,  Tzuan-Horng Liu ,  Tzu-Wei Chiu ,  Kuo-Ching Hsu

IPC分类号： H01L23/58

CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L21/76885 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

摘要： The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.

摘要翻译： 上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。 形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。 钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。 通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。 这种界面电阻的降低导致金属凸块的电阻降低。

公开(公告)号：US20130264684A1

公开(公告)日：2013-10-10

申请号：US13536549

申请日：2012-06-28

申请人： Chen-Hua Yu ,  Der-Chyang Yeh

发明人： Chen-Hua Yu ,  Der-Chyang Yeh

IPC分类号： H01L23/48 ,  H01L21/60 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/2101 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01079 ,  H01L2924/01011 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/03

摘要： Methods and apparatus are disclosed to form a WLP device that comprises a first chip made of a first technology, and a second chip made of a second technology different from the first technology packaged together by a molding material encapsulating the first chip and the second chip. A post passivation interconnect (PPI) line may be formed on the molding material connected to a first contact pad of the first chip by a first connection, and connected to a second contact pad of the second chip by a second connection, wherein the first connection and the second connection may be a Cu ball, a Cu via, a Cu stud, or other kinds of connections.

摘要翻译： 披露了形成WLP装置的方法和装置，该WLP装置包括由第一技术制成的第一芯片和由封装在第一芯片和第二芯片上的模制材料封装在一起的与第一技术不同的第二技术制成的第二芯片。 后钝化互连（PPI）线可以形成在通过第一连接连接到第一芯片的第一接触焊盘的模制材料上，并且通过第二连接连接到第二芯片的第二接触焊盘，其中第一连接 并且第二连接可以是Cu球，Cu通孔，Cu螺柱或其他种类的连接。

公开(公告)号：US20130241083A1

公开(公告)日：2013-09-19

申请号：US13421040

申请日：2012-03-15

申请人： Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung

发明人： Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/49811 ,  H01L21/44 ,  H01L21/441 ,  H01L21/4853 ,  H01L23/48 ,  H01L23/52 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/42 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/1134 ,  H01L2224/13005 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13078 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1411 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48611 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/4911 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83411 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2224/45124 ,  H01L2924/00011 ,  H01L2924/206 ,  H01L2224/05147 ,  H01L2224/05144 ,  H01L2224/05164 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/05552

摘要： Disclosed embodiments include wire joints and methods of forming wire joints that can enable realization of fine pitch joints and collapse control for various packages. A first embodiment is a structure comprising a first substrate, a second substrate, and a wire joint. The first substrate comprises a first bonding surface, and the second substrate comprises a second bonding surface. The first bonding surface is opposite and faces the second bonding surface. The wire joint is attached to and between the first bonding surface and the second bonding surface.

摘要翻译： 公开的实施例包括线接头和形成线接头的方法，其可以实现细间距接头和各种包装件的塌陷控制。 第一实施例是包括第一基板，第二基板和线接头的结构。 第一衬底包括第一接合表面，并且第二衬底包括第二接合表面。 第一接合表面相对并面向第二接合表面。 线接头附接到第一接合表面和第二接合表面之间。

公开(公告)号：US20130221074A1

公开(公告)日：2013-08-29

申请号：US13406198

申请日：2012-02-27

申请人： Cheng-Chang WEI ,  Su-Chun YANG ,  Hsiao-Yun CHEN ,  Chih-Hang TUNG ,  Da-Yuan SHIH ,  Chen-Hua YU

发明人： Cheng-Chang WEI ,  Su-Chun YANG ,  Hsiao-Yun CHEN ,  Chih-Hang TUNG ,  Da-Yuan SHIH ,  Chen-Hua YU

IPC分类号： H05K13/04

CPC分类号： H05K13/0465 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/75252 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2924/00013 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

摘要： A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down.

摘要翻译： 一种方法包括将焊料凸块加热到焊料凸块的熔化温度以上。 焊料凸块被拉伸以增加焊料凸块的高度。 焊锡凸块被冷却。

公开(公告)号：US08500182B2

公开(公告)日：2013-08-06

申请号：US12818022

申请日：2010-06-17

申请人： Ku-Feng Yang ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

发明人： Ku-Feng Yang ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC分类号： B25J15/00

CPC分类号： H01L21/67346 ,  H01L21/6838 ,  H01L21/68785

摘要： An apparatus for supporting a wafer includes a base, and a gas-penetration layer. The gas-penetration layer and a portion of the base directly underlying the gas-penetration layer form a gas passage therebetween. The gas passage is configured to be sealed by the wafer placed directly over the gas-penetration layer. The apparatus further includes a valve connected to the gas passage.

摘要翻译： 用于支撑晶片的装置包括基座和气体穿透层。 气体渗透层和直接位于气体穿透层下方的基底的一部分在它们之间形成气体通道。 气体通道被直接设置在气体穿透层上方的晶片密封。 该装置还包括连接到气体通道的阀。

公开(公告)号：US08476770B2

公开(公告)日：2013-07-02

申请号：US13178345

申请日：2011-07-07

申请人： Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Da-Yuan Shih

发明人： Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Da-Yuan Shih

IPC分类号： H01L23/48

CPC分类号： H01L21/76802 ,  B29C43/04 ,  B29C43/18 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/19 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/83005

摘要： Methods and apparatus for forming through vias in an integrated circuit package are disclosed. An apparatus is disclosed, having a substrate having one or more bond pad terminals for receiving electrical connections on at least one surface; an encapsulation layer covering the at least one surface of the substrate and having a first thickness; a plurality of through vias extending through the encapsulation layer and positioned in correspondence with at least one of the one or more bond pad terminals; conductor material disposed within the plurality of through vias to form electrical connectors within the plurality of through vias; and at least one external terminal disposed on a surface of the encapsulation layer, electrically coupled to one of the one or more bond pad terminals by an electrical connector in at least one of the plurality of through vias. Package arrangements and methods for the through vias are disclosed.

摘要翻译： 公开了用于在集成电路封装中形成通孔的方法和装置。 公开了一种装置，其具有一个基板，该基板具有一个或多个接合焊盘端子，用于在至少一个表面上接收电连接; 覆盖所述衬底的所述至少一个表面并具有第一厚度的封装层; 多个通孔，其延伸穿过所述封装层并且与所述一个或多个接合焊盘端子中的至少一个相对应地定位; 导体材料设置在所述多个通孔内，以在所述多个通孔内形成电连接器; 以及设置在所述封装层的表面上的至少一个外部端子，通过所述多个通孔中的至少一个通孔中的电连接器电耦合到所述一个或多个接合焊盘端子中的一个。 公开了通孔的封装结构和方法。

公开(公告)号：US08455995B2

公开(公告)日：2013-06-04

申请号：US12762085

申请日：2010-04-16

申请人： Po-Hao Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

发明人： Po-Hao Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC分类号： H01L23/04

CPC分类号： H01L23/3121 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00 ,  H01L2224/81805

摘要： A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.

摘要翻译： 一种器件包括具有顶表面和底表面的衬底的插入器。 多个穿通基板通孔（TSV）穿过基板。 多个TSV包括具有第一长度和第一水平尺寸的第一TSV和具有不同于第一长度的第二长度的第二TSV和与第一水平尺寸不同的第二水平尺寸。 互连结构形成在衬底的顶表面上并电耦合到多个TSV。

公开(公告)号：US08450200B2

公开(公告)日：2013-05-28

申请号：US12973707

申请日：2010-12-20

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成金属化层; 在所述半导体衬底和所述金属化层之间形成第一电介质层; 在所述半导体衬底和所述金属化层之间形成第二电介质层，其中所述第二电介质层在所述第一电介质层的上方; 以及形成具有基本上在所述第二介电层中的上部的接触塞和基本在所述第一介电层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处不连续。