公开(公告)号：US20140015122A1

公开(公告)日：2014-01-16

申请号：US13546300

申请日：2012-07-11

Applicant: Meng-Wei Chou ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Meng-Wei Chou ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L23/525 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of forming post passivation interconnects comprises forming a passivation layer over a substrate, wherein a metal pad is embedded in the passivation layer, depositing a first dielectric layer on the passivation layer, applying a first patterning process to the first dielectric layer to form a first opening, forming a first seed layer over the first opening, filling the first opening with a conductive material, depositing a second dielectric layer on the first dielectric layer, applying a second patterning process to the second dielectric layer to form a second opening, forming an under bump metallization structure over the second opening and mounting an interconnect bump over the under bump metallization structure.

Abstract translation: 形成后钝化互连的方法包括在衬底上形成钝化层，其中金属焊盘嵌入钝化层中，在钝化层上沉积第一介电层，将第一图案化工艺应用于第一介电层以形成 第一开口，在第一开口上形成第一种子层，用导电材料填充第一开口，在第一介电层上沉积第二介电层，向第二介电层施加第二图案化工艺以形成第二开口，形成 在第二开口上方的凸块下金属化结构，并且在凸块下金属化结构之上安装互连凸块。

公开(公告)号：US20130334692A1

公开(公告)日：2013-12-19

申请号：US13527422

申请日：2012-06-19

Applicant: Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: B23K31/02 ,  H01L23/488

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/32135 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/81085 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81232 ,  H01L2224/81355 ,  H01L2224/81359 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/06 ,  H01L2924/00

Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Abstract translation: 一种方法包括将第一包装部件的第一电连接器与第二包装部件的第二电连接器对准。 利用第一电​​连接器与第二电连接器对准，金属层被电镀在第一和第二电连接器上。 金属层将第一电连接器连接到第二电连接器。

公开(公告)号：US20130328190A1

公开(公告)日：2013-12-12

申请号：US13492285

申请日：2012-06-08

Applicant: Yi-Wen Wu ,  Ming-Che Ho ,  Wen-Hsiung Lu ,  Chia-Wei Tu ,  Chung-Shi Liu

Inventor： Yi-Wen Wu ,  Ming-Che Ho ,  Wen-Hsiung Lu ,  Chia-Wei Tu ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/06 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06051 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01023 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

公开(公告)号：US20130175685A1

公开(公告)日：2013-07-11

申请号：US13344446

申请日：2012-01-05

Applicant: Yi-Wen Wu ,  Zheng-Yi Lim ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Yi-Wen Wu ,  Zheng-Yi Lim ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: H01L21/768 ,  H01L23/485

CPC classification number: H01L23/485 ,  H01L21/768 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/014

Abstract: A method includes forming a polymer layer over a metal pad, forming an opening in the polymer layer to expose a portion of the metal pad, and forming an under-bump-metallurgy (UBM). The UBM includes a portion extending into the opening to electrically couple to the metal pad.

Abstract translation: 一种方法包括在金属垫上形成聚合物层，在聚合物层中形成开口以暴露金属垫的一部分，并形成凸点下冶金（UBM）。 UBM包括延伸到开口中以电耦合到金属垫的部分。

公开(公告)号：US20120268551A1

公开(公告)日：2012-10-25

申请号：US13442838

申请日：2012-04-09

Applicant: Ben Wu ,  Ming-Che Ho ,  Yuan-Chang Chien

Inventor： Ben Wu ,  Ming-Che Ho ,  Yuan-Chang Chien

IPC: H04N7/15

CPC classification number: H04N19/20 ,  H04N19/46 ,  H04N19/467

Abstract: Before a large amount of information or messages is to be transmitted between image interaction devices, the information or messages are encoded into digital images to generate corresponding digital encoded images. When the digital encoded images are transmitted between the image interaction devices, the information or messages are transmitted along with the digital encoded images without introducing additional data transmission; and as a result, delay between the image interaction devices can be avoided, and real-time operations between the image interaction devices can be achieved.

Abstract translation: 在图像交互装置之前要传送大量的信息或信息之前，信息或消息被编码成数字图像以产生相应的数字编码图像。 当在图像交互装置之间传输数字编码图像时，信息或消息与数字编码图像一起传送而不引入额外的数据传输; 因此，可以避免图像交互装置之间的延迟，并且可以实现图像交互装置之间的实时操作。

公开(公告)号：US20120018878A1

公开(公告)日：2012-01-26

申请号：US12843760

申请日：2010-07-26

Applicant: Ming-Da Cheng ,  MIng-Che Ho ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Cheng-Chung Lin ,  Hui-Jung Tsai ,  Zheng-Yi Lim

Inventor： Ming-Da Cheng ,  MIng-Che Ho ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Cheng-Chung Lin ,  Hui-Jung Tsai ,  Zheng-Yi Lim

IPC: H01L21/288 ,  H01L29/45

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11416 ,  H01L2224/11422 ,  H01L2224/11424 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11822 ,  H01L2224/11827 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/132 ,  H01L2224/13211 ,  H01L2224/13339 ,  H01L2224/13562 ,  H01L2224/13584 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/1379 ,  H01L2224/13794 ,  H01L2224/13809 ,  H01L2224/13813 ,  H01L2224/13817 ,  H01L2224/13818 ,  H01L2224/1382 ,  H01L2224/13849 ,  H01L2224/13855 ,  H01L2224/13857 ,  H01L2224/1386 ,  H01L2224/13866 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/93 ,  H01L2225/06513 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Abstract translation: 形成器件的方法包括提供衬底，以及在衬底上形成焊料凸点。 将次要元件引入邻近焊料凸块顶表面的区域。 然后对焊料凸块执行再流程以将次要元件驱动到焊料凸块中。

公开(公告)号：US20100015894A1

公开(公告)日：2010-01-21

申请号：US12174762

申请日：2008-07-17

Applicant: Ming-Che Ho ,  Jean Wang ,  Lawrence Chiang Sheu

Inventor： Ming-Che Ho ,  Jean Wang ,  Lawrence Chiang Sheu

IPC: B24B1/00 ,  B24B29/00

CPC classification number: B24B37/015 ,  B24B55/02

Abstract: A method for manufacturing integrated circuits on a wafer includes providing a facility-supplied room temperature solution; controlling the temperature of the facility-supplied room temperature solution to a desired temperature set point to generate a rinse solution; and rinsing a polishing pad using the rinse solution. The wafer is then polished by means of a chemical mechanical polishing process.

Abstract translation: 一种用于在晶片上制造集成电路的方法包括提供设备提供的室温解决方案; 将设备供应的室温溶液的温度控制到所需温度设定点以产生漂洗溶液; 并使用冲洗溶液冲洗抛光垫。 然后通过化学机械抛光工艺抛光晶片。

公开(公告)号：US09117772B2

公开(公告)日：2015-08-25

申请号：US13527422

申请日：2012-06-19

Applicant: Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: H01L21/44 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/32135 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/81085 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81232 ,  H01L2224/81355 ,  H01L2224/81359 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/06 ,  H01L2924/00

Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Abstract translation: 一种方法包括将第一包装部件的第一电连接器与第二包装部件的第二电连接器对准。 利用第一电​​连接器与第二电连接器对准，金属层被电镀在第一和第二电连接器上。 金属层将第一电连接器连接到第二电连接器。

公开(公告)号：US08937388B2

公开(公告)日：2015-01-20

申请号：US13492285

申请日：2012-06-08

Applicant: Yi-Wen Wu ,  Ming-Che Ho ,  Wen-Hsiung Lu ,  Chia-Wei Tu ,  Chung-Shi Liu

Inventor： Yi-Wen Wu ,  Ming-Che Ho ,  Wen-Hsiung Lu ,  Chia-Wei Tu ,  Chung-Shi Liu

IPC: H01L23/52

CPC classification number: H01L24/06 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06051 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01023 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

Abstract translation: 公开了用于半导体器件的晶片级封装（WLP）的方法和装置。 电路的接触焊盘可以通过后钝化互连（PPI）线和PPI焊盘连接到焊料凸块。 PPI垫可以包括中空部分和开口。 PPI垫可以与PPI线一起形成为一体。 PPI垫的中空部分可用于控制球安装过程中使用的焊剂量，以便任何额外量的焊剂可以从PPI焊盘的固体部分的开口逸出。 焊锡球可以直接安装到PPI焊盘，而不使用正常的WLP封装所需的任何下凸块金属（UBM）。

公开(公告)号：US08641920B2

公开(公告)日：2014-02-04

申请号：US12482983

申请日：2009-06-11

Applicant: Song-Yuan Chang ,  Ming-Che Ho ,  Ming-hui Lu

Inventor： Song-Yuan Chang ,  Ming-Che Ho ,  Ming-hui Lu

IPC: C09K13/00

CPC classification number: C09K3/1463

Abstract: A polishing composition of the present invention at least comprises about 750 ppm to less than 5000 ppm by weight of abrasive particles, hydrogen peroxide, an accelerator, a dual-corrosion inhibitor and water, wherein the dual-corrosion inhibitor contains a first and a second corrosion inhibitor. The dual-corrosion inhibitor is applied to the planarization of metal layers so as to maintain a high removal rate of metal layers as well as suppress etching of the metal, thus capable of reducing polishing defects such as dishing, erosion and the like.

Abstract translation: 本发明的抛光组合物至少包含约750ppm至小于5000ppm的磨料颗粒，过氧化氢，促进剂，双重腐蚀抑制剂和水，其中双重腐蚀抑制剂包含第一和第二 腐蚀抑制剂。 将双重腐蚀抑制剂应用于金属层的平面化，以保持金属层的高去除率以及抑制金属的蚀刻，从而能够减少抛光缺陷如凹陷，侵蚀等。