公开(公告)号：US20120306097A1

公开(公告)日：2012-12-06

申请号：US13570979

申请日：2012-08-09

申请人： OhHan Kim ,  SungWon Cho ,  DaeSik Choi ,  KyuWon Lee ,  DongSoo Moo

发明人： OhHan Kim ,  SungWon Cho ,  DaeSik Choi ,  KyuWon Lee ,  DongSoo Moo

IPC分类号： H01L23/48

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

摘要： A semiconductor device can include a carrier substrate, and a first semiconductor die disposed on a surface of the carrier substrate. An encapsulant can be disposed over the first semiconductor die and the carrier substrate. The semiconductor device can include first vias disposed through the encapsulant as well as second vias disposed through the encapsulant to expose first contact pads. The first contact pads are on upper surfaces of the first semiconductor die. The semiconductor device can include conductive pillars that fill the first vias, and first conductive metal vias (CMVs) that fill the second vias. The conductive pillar can include a first conductive material, and the first CMVs can be in contact with the first contact pads. The semiconductor device can include a conductive layer disposed over the encapsulant. The conductive layer can electrically connect one of the first CMVs with one of the conductive pillars.

摘要翻译： 半导体器件可以包括载体衬底和设置在载体衬底的表面上的第一半导体管芯。 密封剂可以设置在第一半导体管芯和载体衬底之上。 半导体器件可以包括通过密封剂设置的第一通孔以及通过密封剂设置的第二通孔，以暴露第一接触焊盘。 第一接触垫位于第一半导体管芯的上表面上。 半导体器件可以包括填充第一通孔的导电柱和填充第二通孔的第一导电金属通孔（CMV）。 导电柱可以包括第一导电材料，并且第一CMV可以与第一接触垫接触。 半导体器件可以包括设置在密封剂上的导电层。 导电层可以将第一CMV之一与导电柱之一电连接。

公开(公告)号：US20120211900A1

公开(公告)日：2012-08-23

申请号：US13031546

申请日：2011-02-21

申请人： DaeSik Choi ,  JoonYoung Choi ,  WonIl Kwon

发明人： DaeSik Choi ,  JoonYoung Choi ,  WonIl Kwon

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/0519 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00

摘要： A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.

摘要翻译： 半导体晶片具有接触垫。 在晶片上形成第一绝缘层。 在第一绝缘层和接触垫上形成第二绝缘层。 去除第二绝缘层的一部分以露出接触垫。 第一UBM层形成在第二绝缘层和接触垫的轮廓之上并且跟随第二绝缘层和接触垫的轮廓以在接触垫上产生良好的孔。 在第一UBM层和接触垫上的阱中形成第一缓冲层。 在第一UBM层和第一缓冲层上形成第二UBM层。 在第二UBM层上形成第三UBM层。 在第三UBM层上形成凸块。 第一个缓冲层减少了凸块和接触垫上的应力。 可以在第二和第三UBM层之间形成第二缓冲层。

公开(公告)号：US20110291264A1

公开(公告)日：2011-12-01

申请号：US12791865

申请日：2010-06-01

申请人： DaeSik Choi ,  Taewoo Lee ,  KyuWon Lee ,  SungWon Cho

发明人： DaeSik Choi ,  Taewoo Lee ,  KyuWon Lee ,  SungWon Cho

IPC分类号： H01L23/50 ,  H01L21/56

CPC分类号： H01L24/94 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05147

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor wafer having a chip pad; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer; removing the horizontal cover exposing the underfill and the protruding connector; and singulating an integrated circuit package from the semiconductor wafer.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有芯片焊盘的半导体晶片; 将晶片框架附接到半导体晶片，晶片框架具有与突出连接器成一体的水平盖，突出连接器在芯片垫上; 在所述突出连接器周围和所述水平盖和所述半导体晶片之间形成底部填充物; 移除露出底部填充物和突出连接器的水平盖; 以及从半导体晶片分离集成电路封装。

公开(公告)号：US08067307B2

公开(公告)日：2011-11-29

申请号：US12037291

申请日：2008-02-26

申请人： DaeSik Choi ,  Sang-Ho Lee ,  Soo-San Park

发明人： DaeSik Choi ,  Sang-Ho Lee ,  Soo-San Park

IPC分类号： H01L21/44 ,  H01L23/28

CPC分类号： H01L23/3128 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2223/6677 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit package system comprising: providing a package die; and connecting a connector lead having a first connector end with a protruded connection surface and a lowered structure over the package die.

摘要翻译： 一种集成电路封装系统，包括：提供封装管芯; 以及将具有第一连接器端部的连接器引线与在封装模具上的突出的连接表面和降低的结构连接。

公开(公告)号：US20110260316A1

公开(公告)日：2011-10-27

申请号：US12764805

申请日：2010-04-21

申请人： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

发明人： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

摘要翻译： 半导体器件具有倒装芯片半导体管芯和衬底。 在衬底上形成第一绝缘层。 通过第一绝缘层形成通孔。 导电材料沉积在通孔中以形成导电柱或堆叠的柱状凸块。 导电柱与衬底内的导电层电连接。 在第一绝缘层上形成第二绝缘层。 凸起材料形成在导电柱上。 凸块材料被回流以形成凸块。 去除第一和第二绝缘层。 半导体管芯通过将凸块回流到管芯的导电层而安装到衬底上。 半导体管芯还具有形成在导电层上的第三绝缘层和形成在第一导电层和第三绝缘层上的管芯和UBM的有源表面。

公开(公告)号：US08039275B1

公开(公告)日：2011-10-18

申请号：US12792629

申请日：2010-06-02

申请人： JoHyun Bae ,  DaeSik Choi ,  SungWon Cho

发明人： JoHyun Bae ,  DaeSik Choi ,  SungWon Cho

IPC分类号： H01L21/66

CPC分类号： H01L23/544 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: forming a rounded interconnect on a package carrier having an integrated circuit attached thereto; placing a mold chase having a protrusion over the rounded interconnect; forming an encapsulation over the package carrier, the encapsulation having a recess under the protrusion; removing the mold chase to expose the encapsulation; and removing the encapsulation under the recess for exposing the rounded interconnect.

摘要翻译： 一种制造集成电路封装系统的方法包括：在具有与其连接的集成电路的封装载体上形成圆形互连; 在圆形互连上放置具有突起的模具追逐; 在所述封装载体上形成封装，所述封装在所述突出部下方具有凹部; 去除霉菌以暴露包封; 以及去除凹槽下面的封装以露出圆形互连。

公开(公告)号：US20110089552A1

公开(公告)日：2011-04-21

申请号：US12580933

申请日：2009-10-16

申请人： HyungSang Park ,  DeokKyung Yang ,  DaeSik Choi

发明人： HyungSang Park ,  DeokKyung Yang ,  DaeSik Choi

IPC分类号： H01L25/065 ,  H01L21/50

CPC分类号： H01L23/49816 ,  H01L21/568 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

摘要： A method of manufacture of an integrated circuit packaging system including: forming a top package including: providing a through silicon via interposer having a through silicon via; coupling a stacked integrated circuit die to the through silicon via, and testing a top package; forming a base package including: providing a substrate, coupling a base integrated circuit die to the substrate, and testing a base package; and coupling a stacked interconnect between the top package and the base package.

摘要翻译： 一种集成电路封装系统的制造方法，包括：形成顶部封装，其包括：通过具有通过硅通孔的插入件提供通过硅的通孔; 将堆叠的集成电路管芯耦合到贯穿硅通孔，并测试顶部封装; 形成基本封装，包括：提供基板，将基底集成电路管芯耦合到所述基板，以及测试基底封装; 以及耦合顶部封装和基底封装之间的堆叠互连。

公开(公告)号：US20100279504A1

公开(公告)日：2010-11-04

申请号：US12834176

申请日：2010-07-12

申请人： Heap Hoe Kuan ,  Hamid Eslampour ,  DaeSik Choi ,  Rui Huang ,  Taeg Ki Lim

发明人： Heap Hoe Kuan ,  Hamid Eslampour ,  DaeSik Choi ,  Rui Huang ,  Taeg Ki Lim

IPC分类号： H01L21/768

CPC分类号： H01L21/565 ,  H01L21/561 ,  H01L23/562 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/3511

摘要： A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts and an integrated circuit; providing a structure over the substrate with only a honeycomb meshwork of posts contacting the top surface of the substrate; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that expose the electrical contacts.

摘要翻译： 集成电路封装系统的制造方法包括：向基板提供顶表面; 配置顶表面以包括电触头和集成电路; 在衬底上提供仅具有接触衬底的顶表面的柱的蜂窝状网状结构; 以及沉积材料以防止衬底在衬底的顶表面上以及集成电路上的翘曲，该图案化的材料具有暴露电接触的分立的中空导管。

公开(公告)号：US09252032B2

公开(公告)日：2016-02-02

申请号：US13566872

申请日：2012-08-03

申请人： DaeSik Choi ,  WonJun Ko ,  JaEun Yun

发明人： DaeSik Choi ,  WonJun Ko ,  JaEun Yun

IPC分类号： H01L23/52 ,  H01L21/56 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L21/683

CPC分类号： H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/02371 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/221 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/14364 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.

摘要翻译： 半导体晶片包含多个第一半导体管芯。 半导体晶片安装在载体上。 通过半导体晶片形成通道以分离第一半导体管芯。 第二半导体管芯安装到第一半导体管芯。 密封剂沉积在载体和第一半导体管芯上并进入沟道，同时第二半导体管芯的侧部和表面部分保持暴露于密封剂。 通过通道中的密封剂形成第一导电通孔。 第二导电通孔在第一半导体管芯的接触焊盘上穿过密封剂形成。 在第一和第二导电通孔之间的密封剂之上形成导电层。 在导电层和密封剂之上形成绝缘层。 载体被移除。 互连结构形成在第一导电通孔上。

公开(公告)号：US09190297B2

公开(公告)日：2015-11-17

申请号：US13208027

申请日：2011-08-11

申请人： DaeSik Choi ,  YeongIm Park ,  HyungMin Lee

发明人： DaeSik Choi ,  YeongIm Park ,  HyungMin Lee

IPC分类号： H01L21/50 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L25/16 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L21/565 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01082 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a substrate and first semiconductor die to the substrate. A plurality of vertically-oriented discrete electrical devices, such as a capacitor, inductor, resistor, diode, or transistor, is mounted over the substrate in proximity to the first semiconductor die. A first terminal of the discrete electrical devices is connected to the substrate. A plurality of bumps is formed over the substrate adjacent to the discrete electrical devices. An encapsulant is deposited over and between the first semiconductor die and substrate. A portion of the bumps and a second terminal of the discrete electrical devices is exposed from the encapsulant. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. The semiconductor devices are stackable and electrically connected through the substrate, discrete electrical devices, and bumps. A heat spreader or second semiconductor die can be disposed between the stacked semiconductor devices.

摘要翻译： 半导体器件具有衬底和第一半导体管芯到衬底。 多个垂直取向的分立电气装置，例如电容器，电感器，电阻器，二极管或晶体管，安装在靠近第一半导体管芯的衬底上。 分立电气设备的第一端子连接到基板。 在与分立电气装置相邻的衬底上形成多个凸块。 密封剂沉积在第一半导体管芯和衬底之上和之间。 凸块的一部分和离散电气装置的第二端子从密封剂暴露出来。 在与第一半导体管芯相对的衬底的表面上形成互连结构。 半导体器件可堆叠并通过衬底电连接，分立的电子器件和凸块。 散热器或第二半导体管芯可以设置在堆叠的半导体器件之间。