公开(公告)号：US10068879B2

公开(公告)日：2018-09-04

申请号：US15269576

申请日：2016-09-19

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/34 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

Abstract: An integrated circuit (IC) device is described. The IC device includes a substrate. A connection component including a cavity therethrough is attached to the substrate. A memory die is positioned in the cavity of the connection component and is electrically coupled to the substrate. A logic die extends over the memory die and at least a portion of the connection component, and is electrically coupled to the connection component and the memory die. The connection component is formed free of through silicon vias and is electrically coupled to the substrate through wire bonding.

公开(公告)号：US20180130783A1

公开(公告)日：2018-05-10

申请号：US15343252

申请日：2016-11-04

Applicant: General Electric Company

Inventor： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC: H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81801 ,  H01L2224/8184 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/8309 ,  H01L2224/83091 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1302 ,  H01L2924/13023 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/82

Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

公开(公告)号：US20180130770A1

公开(公告)日：2018-05-10

申请号：US15343248

申请日：2016-11-04

Applicant: General Electric Company

Inventor： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC: H01L25/065 ,  H01L23/485 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/485 ,  H01L2224/18 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An electronics package includes an insulating substrate and electrical components coupled to a first surface of the insulating substrate. A multi-thickness conductor layer is formed on a second surface of the insulating substrate opposite the first surface. The multi-thickness conductor layer extends through vias in the insulating substrate to connect with contact pads of the electrical components. The multi-thickness conductor layer has a first thickness in a region proximate the first electrical component and a second thickness in a region proximate the second electrical component, the first thickness greater than the second thickness. The electronics package also includes a first redistribution layer having a conductor layer formed atop a portion of the multi-thickness conductor layer having the second thickness. A top surface of the conductor layer is co-planar with or substantially co-planar with a top surface of a portion of the multi-thickness conductor layer having the first thickness.

公开(公告)号：US20180082857A1

公开(公告)日：2018-03-22

申请号：US15827199

申请日：2017-11-30

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/14

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

Abstract: An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.

公开(公告)号：US20170373011A1

公开(公告)日：2017-12-28

申请号：US15194775

申请日：2016-06-28

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Risto Ilkka Tuominen

IPC: H01L23/538 ,  H01L21/52 ,  H01L25/065

CPC classification number: H01L23/5389 ,  B81C1/00246 ,  B81C2203/0735 ,  G02B6/4201 ,  G06K19/07745 ,  H01L23/34 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/57 ,  H01L23/58 ,  H01L24/02 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L27/0694 ,  H01L2223/54446 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104

Abstract: A die for a semiconductor chip package includes a first surface including an integrated circuit formed therein. The die also includes a backside surface opposite the first surface. The backside surface has a total surface area defining a substantially planar region of the backside surface. The die further includes at least one device formed on the backside surface. The at least one device includes at least one extension extending from the at least one device beyond the total surface area.

公开(公告)号：US09806051B2

公开(公告)日：2017-10-31

申请号：US14195930

申请日：2014-03-04

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/34 ,  H01L23/538 ,  H05K3/30 ,  H05K3/46 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L25/10 ,  H01L23/42 ,  H01L23/433 ,  H05K1/18 ,  H05K1/02 ,  H05K3/36

CPC classification number: H01L24/32 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/433 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/43 ,  H01L24/45 ,  H01L24/46 ,  H01L24/82 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/2711 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/46 ,  H01L2224/80365 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2225/1052 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/207 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/183 ,  H05K1/185 ,  H05K3/301 ,  H05K3/305 ,  H05K3/306 ,  H05K3/366 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/302 ,  Y02P70/613

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

公开(公告)号：US09704788B2

公开(公告)日：2017-07-11

申请号：US14665735

申请日：2015-03-23

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/433 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

公开(公告)号：US09653438B2

公开(公告)日：2017-05-16

申请号：US14464877

申请日：2014-08-21

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L29/74 ,  H01L31/111 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/4763 ,  H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

Abstract: An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer.

公开(公告)号：US09171785B2

公开(公告)日：2015-10-27

申请号：US14165725

申请日：2014-01-28

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/495 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L21/50

CPC classification number: H01L23/495 ,  H01L21/50 ,  H01L23/3735 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49811 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.

Abstract translation: 公开了一种结合了引线框连接的功率覆盖（POL）封装结构。 该POL结构包括具有电介质层的POL子模块，附着到电介质层的至少一个半导体器件，并且包括由半导体材料构成的衬底和形成在衬底上的多个连接焊盘，以及金属互连 结构电耦合到所述至少一个半导体器件的多个连接焊盘，金属互连结构延伸穿过通过介电层形成的通孔，以便连接到多个连接焊盘。 POL结构还包括电耦合到POL子模块的引线框架，引线框架包括被配置为与外部电路结构互连的引线。

公开(公告)号：US20140264800A1

公开(公告)日：2014-09-18

申请号：US13897685

申请日：2013-05-20

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Abstract translation: 半导体器件模块包括电介质层，具有耦合到电介质层的第一表面的半导体器件和具有耦合到电介质层的第一表面的导电垫片。 半导体器件还包括具有耦合到半导体器件的第二表面的第一表面和导电垫片的第二表面的导电散热器。 金属化层耦合到半导体器件的第一表面和导电垫片的第一表面。 金属化层延伸穿过电介质层，并通过导电垫片和散热器与半导体器件的第二表面电连接。