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    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    31.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20250054849A1

    公开(公告)日：2025-02-13

    申请号：US18779105

    申请日：2024-07-22

    Applicant: Xintec Inc.

    Inventor： Wei-Luen SUEN ,  Po-Jung CHEN ,  Chia-Ming CHENG ,  Po-Shen LIN ,  Jiun-Yen LAI ,  Tsang-Yu LIU ,  Shu-Ming CHANG

    IPC: H01L23/498 ,  H01L21/768 ,  H01L23/15 ,  H01L23/528

    Abstract: A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    32.
    发明公开
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240116751A1

    公开(公告)日：2024-04-11

    申请号：US18480385

    申请日：2023-10-03

    Applicant: Xintec Inc.

    Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG ,  Tsang Yu LIU

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0064 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/0118

    Abstract: A chip package includes an application chip, a micro-electromechanical systems (MEMS) chip, a conductive element, a bonding wire, and a molding compound. The application chip has a conductive pad. The MEMS chip is located on the application chip, and includes a main body and a cap. The main body is located between the cap and the application chip. The main body has a conductive pad. The conductive element is located on the conductive pad of the main body of the MEMS chip. The bonding wire extends from the conductive element to the conductive pad of the application chip. The molding compound is located on the application chip and surrounds the MEMS chip. The conductive element and the bonding wire are located in the molding compound.

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    34.
    发明公开
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20230369371A1

    公开(公告)日：2023-11-16

    申请号：US17744664

    申请日：2022-05-14

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu LIU ,  Chaung-Lin LAI ,  Shu-Ming CHANG

    IPC: H01L27/146 ,  H01L21/48

    CPC classification number: H01L27/14634 ,  H01L21/481 ,  H01L21/4857 ,  H01L27/14627

    Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.

    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
    36.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE 有权
    半导体结构的制造方法

    公开(公告)号：US20150340403A1

    公开(公告)日：2015-11-26

    申请号：US14703796

    申请日：2015-05-04

    Applicant: XINTEC INC.

    Inventor： Yen-Shih HO ,  Shu-Ming CHANG ,  Yung-Tai TSAI ,  Tsang-Yu LIU

    IPC: H01L27/146 ,  H01L21/67 ,  H01L21/683

    CPC classification number: H01L27/14687 ,  H01L21/67092 ,  H01L21/6836 ,  H01L27/14685 ,  H01L31/18

    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A second surface of the wafer is adhered to an ultraviolet tape on a frame, and the temporary bonding layer and the carrier are removed. A protection tape is adhered to the first surface of the wafer. An ultraviolet light is used to irradiate the ultraviolet tape. A dicing tape is adhered to the protection tape and the frame, and the ultraviolet tape is removed. A first cutter is used to dice the wafer from the second surface of the wafer, such that plural chips and plural gaps between the chips are formed. A second cutter with a width smaller than the width of the first cutter is used to cut the protection tape along the gaps.

    Abstract translation: 半导体结构的制造方法包括以下步骤。 临时粘合层用于将载体粘附到晶片的第一表面。 将晶片的第二表面粘附到框架上的紫外线带上，并且移除临时粘合层和载体。 保护带粘附到晶片的第一表面。 使用紫外线照射紫外线带。 切割胶带粘附到保护带和框架上，并且除去紫外线带。 使用第一切割器从晶片的第二表面切割晶片，从而形成芯片之间的多个芯片和多个间隙。 使用宽度小于第一切割器的宽度的第二切割器沿着间隙切割保护带。

    POWER MOSFET PACKAGE
    40.
    发明申请
    POWER MOSFET PACKAGE 有权
    功率MOSFET封装

    公开(公告)号：US20130193520A1

    公开(公告)日：2013-08-01

    申请号：US13828537

    申请日：2013-03-14

    Applicant: Xintec Inc.

    Inventor： Baw-Ching PERNG ,  Ying-Nan WEN ,  Shu-Ming CHANG ,  Ching-Yu NI ,  Yun-Jui HSIEH ,  Wei-Ming CHEN ,  Chia-Lun TSAI ,  Chia-Ming CHENG

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

    Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

    Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

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