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公开(公告)号：US20120306073A1
公开(公告)日：2012-12-06
申请号：US13343582
申请日：2012-01-04
Applicant: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hoa Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
Inventor： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hoa Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
IPC: H01L23/485 , H01L21/768
CPC classification number: H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00
Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
Abstract translation: 一种器件包括具有顶表面的顶部电介质层。 金属柱在顶部介电层的顶表面上具有一部分。 在金属柱的侧壁上形成非润湿层，其中非润湿层不能熔化到熔融焊料上。 焊接区域设置在金属柱上并电耦合到金属柱。
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公开(公告)号：US08105875B1
公开(公告)日：2012-01-31
申请号：US12904835
申请日：2010-10-14
Applicant: Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
Inventor： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC: H01L21/50
CPC classification number: H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
Abstract translation: 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。
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公开(公告)号：US20120001337A1
公开(公告)日：2012-01-05
申请号：US12827563
申请日：2010-06-30
Applicant: Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
Inventor： Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC: H01L23/532 , H01L21/71 , H01L23/522
CPC classification number: H01L23/481 , H01L21/30604 , H01L21/6835 , H01L21/76831 , H01L21/76877 , H01L21/76898 , H01L23/544 , H01L2221/68327 , H01L2223/54426 , H01L2224/13
Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
Abstract translation: 根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。
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公开(公告)号：US20110018069A1
公开(公告)日：2011-01-27
申请号：US12854638
申请日：2010-08-11
Applicant: Jing-Cheng Lin , Chen-Hua Yu
Inventor： Jing-Cheng Lin , Chen-Hua Yu
IPC: H01L27/092
CPC classification number: H01L21/823842 , H01L21/2254 , H01L21/28035 , H01L29/4925 , H01L29/6659
Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.
Abstract translation: 提供半导体器件和制造方法。 介电层形成在衬底上，并且在介电层上形成未掺杂的第一含硅层。 原子层掺杂用于掺杂未掺杂的含硅层。 在第一含硅层上形成第二含硅层。 该过程可以扩展到包括在同一晶片上形成PMOS和NMOS器件。 例如，在原子层掺杂之前，第一含硅层可以在PMOS区中减薄。 在NMOS区域中，去除第一含硅层的掺杂部分，使得NMOS中的第一含硅层的剩余部分未掺杂。 此后，可以使用另一种原子层掺杂工艺将NMOS区域中的第一含硅层掺杂到不同的导电类型。 可以形成掺杂到相应导电类型的第三含硅层。
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55.发明申请公开(公告)号：US20100289116A1
公开(公告)日：2010-11-18
申请号：US12708711
申请日：2010-02-19
Applicant: Jing-Cheng Lin , Chen-Hua Yu
Inventor： Jing-Cheng Lin , Chen-Hua Yu
IPC: H01L29/06
CPC classification number: H01L21/02494 , H01L21/02381 , H01L21/0245 , H01L21/02455 , H01L21/02532 , H01L21/02538 , H01L21/02587 , H01L21/02639 , H01L21/76224 , H01L29/165 , H01L29/267
Abstract: A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.
Abstract translation: 半导体器件包括由第一半导体材料形成的衬底; 基板上有两个绝缘子; 以及半导体区域，其具有在所述两个绝缘体之间并且在所述衬底上的部分。 半导体区域具有与衬底接触并具有倾斜侧壁的底表面。 半导体区域由与第一半导体材料不同的第二半导体材料形成。
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Patent Agency Ranking
公开(公告)号：US10475759B2
公开(公告)日：2019-11-12
申请号：US13270776
申请日：2011-10-11
Applicant: Shin-Puu Jeng , Chen-Hua Yu , Jing-Cheng Lin
Inventor： Shin-Puu Jeng , Chen-Hua Yu , Jing-Cheng Lin
IPC: H01L23/488 , H01L25/11 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065
Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.
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公开(公告)号：US09679783B2
公开(公告)日：2017-06-13
申请号：US13208197
申请日：2011-08-11
Applicant: Jing-Cheng Lin , Chin-Chuan Chang , Jui-Pin Hung , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu
Inventor： Jing-Cheng Lin , Chin-Chuan Chang , Jui-Pin Hung , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu
CPC classification number: H01L21/561 , B29C33/123 , H01L21/566 , H01L23/3121 , H01L24/96 , H01L2924/181 , H01L2924/3511 , H01L2924/00
Abstract: A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.
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公开(公告)号：US08664760B2
公开(公告)日：2014-03-04
申请号：US13343582
申请日：2012-01-04
Applicant: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
Inventor： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
CPC classification number: H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00
Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
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公开(公告)号：US20140027872A1
公开(公告)日：2014-01-30
申请号：US13558063
申请日：2012-07-25
Applicant: Chen-Hua Yu , Wen-Chih Chiou , Jing-Cheng Lin
Inventor： Chen-Hua Yu , Wen-Chih Chiou , Jing-Cheng Lin
IPC: H01L31/0232 , H01L31/18
CPC classification number: H01L27/14689 , H01L21/6835 , H01L21/76834 , H01L21/76879 , H01L21/76898 , H01L23/481 , H01L24/13 , H01L27/1462 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14685 , H01L27/14687 , H01L31/02002 , H01L31/02327 , H01L2221/68327 , H01L2221/6834 , H01L2224/023 , H01L2224/13101 , H01L2924/014 , H01L2924/00014
Abstract: A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.
Abstract translation: 一种器件包括半导体衬底，在半导体衬底的前表面处的图像传感器和图像传感器上的多个电介质层。 滤色器和微透镜设置在多个介电层上并与图像传感器对准。 穿通通孔穿过半导体衬底。 再分配线（RDL）设置在多个介电层上，其中RDL电连接到通孔。 聚合物层覆盖RDL。
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公开(公告)号：US20140001645A1
公开(公告)日：2014-01-02
申请号：US13619877
申请日：2012-09-14
Applicant: Jing-Cheng Lin , Chen-Hua Yu
Inventor： Jing-Cheng Lin , Chen-Hua Yu
CPC classification number: H01L25/0652 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/76898 , H01L23/3135 , H01L23/3171 , H01L23/49816 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/81 , H01L24/92 , H01L24/96 , H01L25/03 , H01L25/0657 , H01L25/50 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/05655 , H01L2224/05666 , H01L2224/11002 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/12105 , H01L2224/13023 , H01L2224/13024 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/14134 , H01L2224/14144 , H01L2224/14154 , H01L2224/14164 , H01L2224/14181 , H01L2224/17181 , H01L2224/2919 , H01L2224/73204 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/81895 , H01L2224/83104 , H01L2224/9202 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06568 , H01L2924/15787 , H01L2924/181 , H01L2924/18162 , H01L2924/351 , H01L2224/11 , H01L2924/00014 , H01L2224/03 , H01L2224/81 , H01L2924/00 , H01L2924/014 , H01L2924/0665
Abstract: A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.
Abstract translation: 提供了一种三维堆叠半导体器件的系统和方法。 在一个实施例中，将两个或更多个半导体管芯附着到载体并封装。 两个或更多个半导体管芯的连接被暴露，并且两个或更多个半导体管芯可以被薄化以在相对侧上形成连接。 然后可以将另外的半导体管芯置于偏移或悬垂位置中。
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