公开(公告)号：US20090267213A1

公开(公告)日：2009-10-29

申请号：US12384977

申请日：2009-04-09

申请人： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

发明人： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

IPC分类号： H01L23/488 ,  H01L23/18

CPC分类号： H01L23/49816 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/06136 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

摘要翻译： 提供了一种新的方法和封装，用于安装已经提供有小间距输入/输出互连凸块的半导体器件。 由柱状金属和焊料凸点组成的细间距焊料凸块直接施加到半导体器件的I / O焊盘，然后将器件倒装芯片接合到基板上。 可以为设备的I / O焊盘布置以便需要对器件的附加机械支撑的情况下提供虚拟凸块。

公开(公告)号：US07569422B2

公开(公告)日：2009-08-04

申请号：US11836816

申请日：2007-08-10

申请人： Mou-Shiung Lin

发明人： Mou-Shiung Lin

IPC分类号： H01L21/00

CPC分类号： H01L23/293 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/0231 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/82 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a glue material, next forming a polymer material on the substrate, on the semiconductor chip, and on the metal bump, next polishing the polymer material, next forming a patterned circuit layer over the polymer material and connected to the metal bump, and then forming a tin-containing ball over the patterned circuit layer and connected to the patterned circuit layer.

摘要翻译： 制造芯片封装的方法包括：向半导体芯片提供金属凸块，接下来使用胶合材料将半导体芯片粘附到基板上，接着在半导体芯片上形成聚合物材料，在半导体芯片上形成聚合物材料，然后在金属凸块上形成 抛光聚合物材料，接下来在聚合物材料上形成图案化的电路层并连接到金属凸块，然后在图案化的电路层上形成含锡球并连接到图案化的电路层。

公开(公告)号：US07534718B2

公开(公告)日：2009-05-19

申请号：US11927721

申请日：2007-10-30

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L21/4763

CPC分类号： H01L23/60 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/62 ,  H01L24/05 ,  H01L27/0248 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

摘要翻译： 提供了一种创建互连线的方法。 细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。 钝化层沉积在电介质层上，在钝化层的表面上形成厚的第二层电介质。 在厚的第二层电介质中产生厚而宽的互连线。 也可以消除第一层电介质，在已​​经沉积在衬底的表面上的钝化层的表面上产生宽厚的互连网络。

公开(公告)号：US20090065937A1

公开(公告)日：2009-03-12

申请号：US12269064

申请日：2008-11-12

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/488

CPC分类号： H01L25/50 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05624 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.

摘要翻译： 实现了制造芯片封装的方法。 在硅晶片上形成晶种层。 在种子层上形成光致抗蚀剂层，光致抗蚀剂层中的开口露出种子层。 在由开口暴露的种子层上形成第一焊料凸块。 去除光致抗蚀剂层。 不在第一焊料凸块下面的种子层被去除。 芯片上的第二焊料凸点与第一焊料凸块接合。

公开(公告)号：US20090057894A1

公开(公告)日：2009-03-05

申请号：US12262195

申请日：2008-10-31

申请人： Chiu-Ming Chou ,  Mou-Shiung Lin

发明人： Chiu-Ming Chou ,  Mou-Shiung Lin

IPC分类号： H01L23/498

CPC分类号： H01L24/13 ,  H01L23/53238 ,  H01L23/53252 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first metal layer exposed by an opening in said first mask layer. Said first mask layer is removed. A second mask layer is deposited over said second metal layer. A third metal layer is deposited over said second metal layer exposed by an opening in said second mask layer. Said second mask layer is removed. Said first metal layer not covered by said second metal layer is removed.

摘要翻译： 一种用于制造多个金属层的方法包括以下步骤。 电子元件设有多个接触点。 第一金属层沉积在所述电子部件上。 第一掩模层沉积在所述第一金属层上。 在由所述第一掩模层中的开口暴露的所述第一金属层上沉积第二金属层。 去除所述第一掩模层。 第二掩模层沉积在所述第二金属层上。 第三金属层沉积在由所述第二掩模层中的开口暴露的所述第二金属层上。 去除所述第二掩模层。 除去未被所述第二金属层覆盖的所述第一金属层。

公开(公告)号：US20090011542A1

公开(公告)日：2009-01-08

申请号：US12206754

申请日：2008-09-09

申请人： Jin-Yuan Lee ,  Ching-Cheng Huang ,  Mou-Shiung Lin

发明人： Jin-Yuan Lee ,  Ching-Cheng Huang ,  Mou-Shiung Lin

IPC分类号： H01L21/50

CPC分类号： H01L23/293 ,  H01L23/3114 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

公开(公告)号：US20090001511A1

公开(公告)日：2009-01-01

申请号：US12208353

申请日：2008-09-11

申请人： Mou-Shiung Lin

发明人： Mou-Shiung Lin

IPC分类号： H01L29/00

CPC分类号： H01L23/5227 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/16 ,  H01L2924/3011

摘要： The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

公开(公告)号：US07470997B2

公开(公告)日：2008-12-30

申请号：US10796427

申请日：2004-03-09

申请人： Mou-Shiung Lin ,  Michael Chen ,  Chien Kang Chou ,  Mark Chou

发明人： Mou-Shiung Lin ,  Michael Chen ,  Chien Kang Chou ,  Mark Chou

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53252 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

摘要： In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps.

摘要翻译： 在本发明中，与金属盖的铜互连延伸到后钝化互连处理。 金属盖可以是铝。 可以在金属盖上形成金焊盘以允许引线接合和测试应用。 可以在集成电路上形成各种后钝化无源部件，并通过金属盖连接。

公开(公告)号：US20080241992A1

公开(公告)日：2008-10-02

申请号：US12109367

申请日：2008-04-25

申请人： Mou-Shiung Lin ,  Shih-Hsiung Lin

发明人： Mou-Shiung Lin ,  Shih-Hsiung Lin

IPC分类号： H01L21/60 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81011 ,  H01L2224/92247 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2224/45099

摘要： A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

摘要翻译： 一种组装芯片的方法。 提供第一芯片和第二芯片。 在第一芯片上形成至少一个导电柱，并且在导电柱上形成导电连接材料。 第二芯片还包括至少一个导电柱。 第一芯片经由导电柱和导电连接材料连接到第二芯片。

公开(公告)号：US07425764B2

公开(公告)日：2008-09-16

申请号：US11840242

申请日：2007-08-17

申请人： Mou-Shiung Lin

发明人： Mou-Shiung Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/74

CPC分类号： H01L24/12 ,  H01L21/768 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/60 ,  H01L24/11 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10T428/12542 ,  Y10T428/12993 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.