公开(公告)号：US09355971B1

公开(公告)日：2016-05-31

申请号：US14747787

申请日：2015-06-23

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Shekar Mallikarjunaswamy

IPC分类号： H01L29/00 ,  H01L23/62 ,  H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L29/73 ,  H01L29/744 ,  H01L49/02

CPC分类号： H01L28/20 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/53257 ,  H01L27/0288 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/7304 ,  H01L29/7436 ,  H01L29/744 ,  H01L2924/0002 ,  H01L2924/00

摘要： In some embodiment, a fuse structure in a semiconductor device uses a metal fuse element connected to a stacked via fuse link connected to a thin film resistive element. The fuse structure can be incorporated in an integrated circuit for EOS protection. In other embodiments, an integrated EOS/ESD protection circuit includes a current limiting resistor integrated with an ESD protection circuit. In some embodiments, the current limiting resistor is formed in an N-well forming the collector of the ESD protection circuit.

摘要翻译： 在一些实施例中，半导体器件中的熔丝结构使用连接到连接到薄膜电阻元件的堆叠通孔熔丝链的金属熔丝元件。 保险丝结构可以集成在用于EOS保护的集成电路中。 在其它实施例中，集成EOS / ESD保护电路包括与ESD保护电路集成的限流电阻。 在一些实施例中，限流电阻形成在形成ESD保护电路的集电极的N阱中。

公开(公告)号：US09355953B2

公开(公告)日：2016-05-31

申请号：US14518845

申请日：2014-10-20

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Tao Feng ,  Anup Bhalla

IPC分类号： H01L29/66 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

CPC分类号： H01L23/49844 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/66734 ,  H01L29/781 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging. The projected footprint of extended support ledge onto the major SCS plane can essentially enclose the correspondingly projected footprint of SEDE.

摘要翻译： 公开了一种具有基板侧暴露的器件侧电极（SEDE）的半导体器件。 半导体器件在器件侧具有器件侧，衬底侧和半导体器件区（SDR）的半导体衬底（SCS）。 形成器件侧电极（DSE）用于器件操作。 通过衬底沟槽（TST）延伸通过SCS，达到DSE将其变成SEDE。 SEDE可以通过TST通过导电互连器相互连接。 可以包括在SSE上面的衬底侧电极（SSE）和窗口化的衬底侧钝化（SSPV）。 SSPV定义了在设备封装期间扩展焊料材料的SSE区域。 可以包括下面覆盖SEDE的器件侧的器件侧钝化（DSPV）。 DSE还可以包括在SEDE下面堆叠的扩展支撑凸缘，用于在晶片间加工包装期间对其进行结构支持。 延伸支撑突出到主SCS平面上的预计占地面积基本上可以包围SEDE相应的预计占地面积。

公开(公告)号：US09312381B1

公开(公告)日：2016-04-12

申请号：US14747925

申请日：2015-06-23

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Lingpeng Guan ,  Karthik Padmanabhan ,  Hamza Yilmaz

IPC分类号： H01L29/94 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7816

摘要： A lateral superjunction MOSFET device includes a gate structure, a first column connected to the lateral superjunction structure and a second column disposed in close proximity to the first column. The lateral superjunction MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the lateral superjunction MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.

摘要翻译： 横向超结MOSFET器件包括栅极结构，连接到横向超结结构的第一列和靠近第一列设置的第二列。 横向超结MOSFET器件包括第一列，以在MOSFET导通时接收来自沟道的电流，并且将沟道电流分配到用作漏极漂移区的侧向超结构结构。 设置在第一列附近的第二列用于在MOSFET器件关闭时夹紧第一列，并阻止由漏极端子处的MOSFET器件持续的高电压到达栅极结构。 在一些实施例中，横向超结MOSFET设备还包括用于漏极，源极和体接触掺杂区域指的端接结构。

公开(公告)号：US09281416B2

公开(公告)日：2016-03-08

申请号：US14486391

申请日：2014-09-15

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Daniel Calafut ,  Yi Su ,  Jongoh Kim ,  Hong Chang ,  Hamza Yilmaz ,  Daniel S. Ng

IPC分类号： H01L29/872 ,  H01L27/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/78 ,  H01L29/47 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/06 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/872

摘要： A Schottky diode includes first and second trenches formed in a semiconductor layer where the first and second trenches are lined with a thin dielectric layer and filled partially with a trench conductor layer with the remaining portion being filled with a first dielectric layer. Well regions are formed spaced-apart in a top portion of the semiconductor layer between the first and second trenches. A Schottky metal layer is formed on a top surface of the semiconductor layer between the first and second trenches. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.

摘要翻译： 肖特基二极管包括形成在半导体层中的第一和第二沟槽，其中第一和第二沟槽衬有薄介电层，并部分地填充有沟槽导体层，其余部分填充有第一介电层。 阱区在第一和第二沟槽之间的半导体层的顶部部分间隔开形成。 在第一和第二沟槽之间的半导体层的顶表面上形成肖特金属层。 肖特基二极管由肖特基金属层作为阳极形成，第一和第二沟槽之间的半导体层作为阴极形成。 第一和第二沟槽中的沟槽导体层电连接到肖特基二极管的阳极。 在一个实施例中，肖特基二极管与同一半导体衬底上的沟槽场效应晶体管集成。

公开(公告)号：US09269805B2

公开(公告)日：2016-02-23

申请号：US14838203

申请日：2015-08-27

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Sik Lui

IPC分类号： H01L21/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L21/265 ,  H01L29/423 ,  H01L21/266 ,  H01L29/10

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66704 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7825

摘要： Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有沟道长度的沟槽MOSFET，沟道长度可以通过对体内 - 漏极结的反掺杂来形成与沟槽相邻的分支区域来控制。 通道长度限定在底部的分段区域和顶部的源区域之间。 分裂区域和源区域都具有相同的导电类型，尽管它们可以是不同的离子种类。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US09265121B2

公开(公告)日：2016-02-16

申请号：US14064064

申请日：2013-10-25

申请人： Gilbert S. Lee

发明人： Gilbert S. Lee

IPC分类号： H05B33/08

CPC分类号： H05B33/0896

摘要： An efficient, cost effective power driver for OLED panels is configured with a small BOM without compromising the display quality. The power driver adopts only one Inverting Buck-Boost Converter (IBBC) to regulate the necessary output voltage for the OLED panel load. The output voltage to drive the OLED panel load is supplied by the IBBC and the positive input of the OLED panel is tied into the input power supply of VIN directly without any switch. A DC-DC converter is provided to generate a reference ground and drive the associated control circuits. The input DC voltage VIN is utilized as a reference voltage for both the IBBC and the DC-DC converter.

摘要翻译： 用于OLED面板的高效率，高性价比的电源驱动器配置有小型BOM，而不会影响显示质量。 功率驱动器仅采用一个反相降压 - 升压转换器（IBBC）来调节OLED面板负载的必要输出电压。 驱动OLED面板负载的输出电压由IBBC提供，OLED面板的正极输入端直接连接到VIN的输入电源，无需任何开关。 提供DC-DC转换器以产生参考地并驱动相关联的控制电路。 输入直流电压VIN用作IBBC和DC-DC转换器的参考电压。

公开(公告)号：US09252265B2

公开(公告)日：2016-02-02

申请号：US14660361

申请日：2015-03-17

申请人： ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L21/283 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L21/265 ,  H01L29/45 ,  H01L29/49 ,  H01L29/10

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

公开(公告)号：US09252239B2

公开(公告)日：2016-02-02

申请号：US14292880

申请日：2014-05-31

申请人： Hamza Yilmaz ,  John Chen ,  Daniel Ng ,  Wenjun Li

发明人： Hamza Yilmaz ,  John Chen ,  Daniel Ng ,  Wenjun Li

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L21/26586 ,  H01L21/823487 ,  H01L27/0255 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/872 ,  H01L29/8725

摘要： This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

摘要翻译： 本发明公开了一种半导体功率器件，其包括设置在半导体衬底的顶表面附近的多个顶部电端子。 顶部电气端子中的每一个包括在半导体衬底的顶表面附近形成为硅化物接触层的端子接触层。 半导体功率器件的沟槽栅极从半导体衬底的顶表面打开，并且每个沟槽栅极包括被配置为硅化物接触层的硅化物层，硅化物层设置在略微低于 半导体衬底的顶表面围绕沟槽栅极。

公开(公告)号：US09245949B2

公开(公告)日：2016-01-26

申请号：US14561172

申请日：2014-12-04

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108 ,  H01L29/74 ,  H01L31/111 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872 ,  H01L21/265 ,  H01L29/08 ,  H01L29/36 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L29/0886 ,  H01L21/26586 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/365 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/8725

摘要： Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a semiconductor layer on a semiconductor substrate of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the semiconductor layer. The semiconductor device includes a first epitaxial layer formed on sidewalls of the trenches where the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions. In another embodiment, a semiconductor device is formed in a first semiconductor layer having trenches and mesas formed thereon where the trenches extend from the top surface to the bottom surface of the first semiconductor layer. The semiconductor device includes semiconductor regions formed on the bottom surface of the mesas of the first semiconductor layer.

摘要翻译： 使用形成在介质填充沟槽的侧壁上的薄外延层（纳米管）来形成半导体器件。 在一个实施例中，半导体器件形成在具有相反导电类型的半导体衬底上的半导体层中，并且其中形成有沟槽，其中沟槽从半导体层的顶表面延伸到底表面。 半导体器件包括形成在沟槽的侧壁上的第一外延层，其中第一外延层基本上与相邻半导体区域电荷平衡。 在另一个实施例中，半导体器件形成在其上形成有沟槽和台面的第一半导体层中，其中沟槽从第一半导体层的顶表面延伸到底表面。 半导体器件包括形成在第一半导体层的台面的底表面上的半导体区域。

公开(公告)号：US09230949B2

公开(公告)日：2016-01-05

申请号：US14641351

申请日：2015-03-07

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L23/495 ,  H01L25/07 ,  H01L23/492 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/367 ,  H01L25/065 ,  H01L23/433

CPC分类号： H01L25/50 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/27 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/07 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/118 ,  H01L2224/13022 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the metal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

摘要翻译： 堆叠多芯片封装结构包括引线框架，安装在引线框架上的第一半导体芯片，安装在引线框架上的第二半导体芯片翻转芯片，安装在第一和第二半导体芯片顶部的金属夹子和 第三半导体芯片堆叠在金属夹上; 将第三半导体芯片上的电极电连接到第一和第二半导体芯片和引线框架的引脚的接合线; 塑料成型封装引线框架，芯片和金属夹。