公开(公告)号：US20230197679A1

公开(公告)日：2023-06-22

申请号：US17558457

申请日：2021-12-21

申请人： Intel Corporation

发明人： Jeremy Ecton ,  Jason M. Gamba ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Xiaoxuan Sun ,  Omkar G. Karhade ,  Xavier Francois Brun ,  Yonggang Li ,  Suddhasattwa Nad ,  Bohan Shan ,  Haobo Chen ,  Gang Duan

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L25/0652 ,  H01L24/16 ,  H01L24/14 ,  H01L24/73 ,  H01L24/13 ,  H01L23/5383 ,  H01L2224/16227 ,  H01L2224/14177 ,  H01L2224/73204 ,  H01L2224/13111 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01031

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

公开(公告)号：US09837370B2

公开(公告)日：2017-12-05

申请号：US15263162

申请日：2016-09-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Jing-Cheng Lin

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/17 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13564 ,  H01L2224/1412 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/381

摘要： A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures.

公开(公告)号：US09831208B2

公开(公告)日：2017-11-28

申请号：US14787654

申请日：2015-03-10

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Liang Cheng ,  Peng Qi ,  Lu Zheng

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/17 ,  H01L24/14 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14177 ,  H01L2924/12041 ,  H01L2924/15788 ,  H01L2924/3511

摘要： A driving chip and a display device, relating to the technical field of driving chip for displays, are disclosed. A surface of the driving chip has a first edge and a second edge opposite to each other. The driving chip includes connecting bumps and supporting bumps, which are arranged along the first edge to form at least one first bump column, and at either end of the first bump column, there is at least one of the supporting bumps; the connecting bumps and the supporting bumps are arranged along the second edge to form at least one second bump column, and at either end of the second bump column, there is at least one of the supporting bumps. A surface of the driving chip according to embodiments of the invention has bump columns, a supporting bump is disposed at an end of a bump column, and acts to support the driving chip favorably. Thus, upon bonding and packaging, the driving chip can bear a force in equilibrium as a whole, and occurrence of a problem of impression defectiveness is avoided.

公开(公告)号：US20170309571A1

公开(公告)日：2017-10-26

申请号：US15413713

申请日：2017-01-24

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Moon Hee YI ,  Joo Hwan JUNG ,  Yul Kyo CHUNG

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC分类号： H01L23/5389 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/14 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14177 ,  H01L2224/19 ,  H01L2224/215 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H01L2924/3025

摘要： A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.

公开(公告)号：US20170221934A1

公开(公告)日：2017-08-03

申请号：US15412740

申请日：2017-01-23

申请人： Japan Display Inc.

发明人： Yohei IWAI ,  Ryosuke Imaseki

IPC分类号： H01L27/12 ,  H01L23/00

CPC分类号： H01L27/1244 ,  G02F1/13452 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/1368 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/14165 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/17517 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/1426

摘要： A display device made of a TFT substrate and a driver IC is configured to eliminate bad connection between them. On the driver IC connected to the TFT substrate, a first principal surface has first bumps formed along a first side having a first edge and second bumps formed along a second side opposite to the first side and having a second edge. The TFT substrate has first terminals and second terminals connected to the first and the second bumps, respectively. On a cross section taken perpendicularly to the first and the second sides, the first principal surface has a first area between the first and the second bumps and a second area between the second bumps and the second edge. The first and the second areas are bent toward the TFT substrate.

公开(公告)号：US09673161B2

公开(公告)日：2017-06-06

申请号：US15212970

申请日：2016-07-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hong Cha ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tsung-Hsien Chiang ,  Hao-Juin Liu ,  Yao-Chun Chuang ,  Chita Chuang

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

CPC分类号： H01L24/17 ,  H01L21/76897 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/1301 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13601 ,  H01L2224/141 ,  H01L2224/14152 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16505 ,  H01L2224/171 ,  H01L2224/17104 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/3841

摘要： The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

公开(公告)号：US20170125359A1

公开(公告)日：2017-05-04

申请号：US15299339

申请日：2016-10-20

申请人： FUJITSU LIMITED

发明人： Taiji Sakai ,  Seiki Sakuyama ,  Nobuhiro Imaizumi ,  Aki Dote

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/4012 ,  H01L23/538 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/98 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/117 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/14177 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17134 ,  H01L2224/17177 ,  H01L2224/17505 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81065 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/00 ,  H01L2021/60022 ,  H01L2225/06513 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

摘要： An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

公开(公告)号：US20170092609A1

公开(公告)日：2017-03-30

申请号：US15271405

申请日：2016-09-21

申请人： Renesas Electronics Corporation

发明人： Akira YAJIMA

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05664 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14517 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01022 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2924/01073 ,  H01L2924/0496 ,  H01L2924/01046 ,  H01L2924/01044 ,  H01L2924/01078 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00

摘要： In the semiconductor device, a bump electrode which connects a semiconductor chip and a wiring board is made up of a first part surrounded by an insulating film and a second part exposed from the insulating film. Since it is possible to reduce a width of the bump electrode while increasing a height of the bump electrode, a distance between the neighboring bump electrodes can be increased, and a filling property of a sealing material can be improved.

公开(公告)号：US20170077049A1

公开(公告)日：2017-03-16

申请号：US15120370

申请日：2014-03-26

申请人： Mitsubishi Electric Corporation

发明人： Takeshi YUASA ,  Kiyoshi ISHIDA ,  Yoshihiro TSUKAHARA ,  Kohei NISHIGUCHI

IPC分类号： H01L23/66 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528

CPC分类号： H01L23/66 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2223/6683 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14156 ,  H01L2224/14177 ,  H01L2224/14515 ,  H01L2224/16227 ,  H05K1/0243 ,  H05K2201/10674 ,  H01L2924/00012

摘要： A surface mount high-frequency circuit is configured such that a plurality of ground pads 41 and a plurality of external connection ground conductors 51 are discretely disposed to surround a signal line pad 42 and an external connection signal line conductor 52, and a plurality of interlayer connection ground conductors 31 and that a plurality of columnar ground conductors 12 are discretely disposed to surround an interlayer connection signal line conductor 32. Thus, it is possible to suppress radiation of an unnecessary signal to the outside using a simple production process that is completed by only a wafer process without separately preparing a component such as a shield cover case.

摘要翻译： 表面安装高频电路被配置为使得多个接地焊盘41和多个外部连接接地导体51离散地设置成围绕信号线焊盘42和外部连接信号线导体52以及多个中间层 连接接地导体31和多个柱状接地导体12离散地设置成围绕层间连接信号线导体32.因此，可以使用简单的生产过程来抑制对外部的不必要信号的辐射，该简单的生产过程由 仅仅是晶片工艺，而不需要单独地制备诸如屏蔽罩壳的部件。

公开(公告)号：US20170018523A1

公开(公告)日：2017-01-19

申请号：US15263162

申请日：2016-09-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Jing-Cheng Lin

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

CPC分类号： H01L24/17 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13564 ,  H01L2224/1412 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/381

摘要： A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures.

摘要翻译： 多芯片封装包括具有多个第一凸块结构的基板。 多个第一凸块结构的第一凸块结构之间的间距在基板的表面上是均匀的。 多芯片封装包括结合到衬底的第一芯片和与衬底结合的第二芯片。 第一芯片包括多个第二凸块结构，并且多个第二凸块结构被结合到多个第一凸块结构的第一组第一凸块结构。 第二芯片包括多个第三凸块结构，并且多个第三凸起结构被结合到多个第一凸块结构的第二组第一凸块结构。 多个第二凸块结构的第二凸块结构之间的间距与多个第三凸块结构中的第三凸起结构之间的间距不同。