公开(公告)号：US20190007200A1

公开(公告)日：2019-01-03

申请号：US15638162

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Neel Shah ,  Kirk S. Yap ,  Amy L. Santoni ,  Michael Neve de Mevergnies ,  Oscar Mendoza ,  Sreejit Chakravarty ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici

IPC: H04L9/08 ,  G01R31/317 ,  G01R31/26 ,  H04L9/06

Abstract: A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.

公开(公告)号：US10158484B2

公开(公告)日：2018-12-18

申请号：US15289819

申请日：2016-10-10

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G09C1/00 ,  G06F9/30 ,  G06F9/38

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

公开(公告)号：US10127042B2

公开(公告)日：2018-11-13

申请号：US15396578

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F9/30 ,  G06F21/60 ,  G06F15/80 ,  G06F9/38 ,  G06F12/0897 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US10103877B2

公开(公告)日：2018-10-16

申请号：US14864227

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Kirk S. Yap ,  Vinodh Gopal

IPC: G06F9/30 ,  G06F21/60 ,  H04L9/28 ,  H04L9/06 ,  H04L9/14

Abstract: A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic identifies one or more constant bits of an output bit sequence. The processing logic generates a plurality of variable bits of the output bit sequence. The processing logic produces the output bit sequence including the identified constant bits and the generated plurality of variable bits.

公开(公告)号：US09996708B2

公开(公告)日：2018-06-12

申请号：US14751995

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Kirk S. Yap ,  Vinodh Gopal

IPC: G06F11/30 ,  G06F12/14 ,  G06F21/74 ,  G09C1/00 ,  H04L9/06

CPC classification number: G06F21/74 ,  G06F21/73 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a data register having a plurality of data bits and a key register having a plurality of key bits. The hardware accelerator also includes a data mode selector module to select one of an encrypt mode or a decrypt mode for processing the plurality of data bits. The hardware accelerator further includes a key mode selector module to select one of the encrypt mode or the decrypt mode for processing the plurality of key bits.

公开(公告)号：US20180150471A1

公开(公告)日：2018-05-31

申请号：US15719774

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Kirk S. Yap ,  Simon N. Peffers ,  Daniel F. Cutter

IPC: G06F17/30 ,  H03M7/30

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

Abstract: Technologies for database acceleration include a computing device having a database accelerator. The database accelerator performs a decompress operation on one or more compressed elements of a compressed database to generate one or more decompressed elements. After decompression of the compressed elements, the database accelerator prepares the one or more decompressed elements to generate one or more prepared elements to be processed by an accelerated filter. The database accelerator then performs the accelerated filter on the one or more prepared elements to generate one or more output elements. Other embodiments are described and claimed.

公开(公告)号：US20180026651A1

公开(公告)日：2018-01-25

申请号：US15473748

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  Daniel F. Cutter ,  James D. Guilford ,  Kirk S. Yap

IPC: H03M7/30 ,  H03M7/40 ,  G06F12/0893

CPC classification number: H04Q11/0005 ,  B25J15/0014 ,  B65G1/0492 ,  G02B6/3882 ,  G02B6/3893 ,  G02B6/3897 ,  G02B6/4292 ,  G02B6/4452 ,  G05D23/1921 ,  G05D23/2039 ,  G06F1/183 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0688 ,  G06F3/0689 ,  G06F8/65 ,  G06F9/4401 ,  G06F9/5016 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5072 ,  G06F9/5077 ,  G06F11/141 ,  G06F11/3414 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/10 ,  G06F12/109 ,  G06F12/1408 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/409 ,  G06F13/42 ,  G06F13/4282 ,  G06F15/8061 ,  G06F17/30949 ,  G06F2209/5019 ,  G06F2209/5022 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/7207 ,  G06Q10/06 ,  G06Q10/06314 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  G07C5/008 ,  G08C17/02 ,  G08C2200/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1072 ,  G11C11/56 ,  G11C14/0009 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/3086 ,  H03M7/40 ,  H03M7/4031 ,  H03M7/4056 ,  H03M7/4081 ,  H03M7/6005 ,  H03M7/6023 ,  H04B10/25 ,  H04B10/2504 ,  H04L9/0643 ,  H04L9/14 ,  H04L9/3247 ,  H04L9/3263 ,  H04L12/2809 ,  H04L29/12009 ,  H04L41/024 ,  H04L41/046 ,  H04L41/0813 ,  H04L41/082 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/145 ,  H04L41/147 ,  H04L41/5019 ,  H04L43/065 ,  H04L43/08 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L43/16 ,  H04L45/02 ,  H04L45/52 ,  H04L47/24 ,  H04L47/765 ,  H04L47/782 ,  H04L47/805 ,  H04L47/82 ,  H04L47/823 ,  H04L49/15 ,  H04L49/25 ,  H04L49/357 ,  H04L49/45 ,  H04L49/555 ,  H04L67/02 ,  H04L67/10 ,  H04L67/1004 ,  H04L67/1008 ,  H04L67/1012 ,  H04L67/1014 ,  H04L67/1029 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/12 ,  H04L67/16 ,  H04L67/306 ,  H04L67/34 ,  H04L69/04 ,  H04L69/329 ,  H04Q1/04 ,  H04Q11/00 ,  H04Q11/0003 ,  H04Q11/0062 ,  H04Q11/0071 ,  H04Q2011/0037 ,  H04Q2011/0041 ,  H04Q2011/0052 ,  H04Q2011/0073 ,  H04Q2011/0079 ,  H04Q2011/0086 ,  H04Q2213/13523 ,  H04Q2213/13527 ,  H04W4/023 ,  H04W4/80 ,  H05K1/0203 ,  H05K1/181 ,  H05K5/0204 ,  H05K7/1418 ,  H05K7/1421 ,  H05K7/1422 ,  H05K7/1447 ,  H05K7/1461 ,  H05K7/1485 ,  H05K7/1487 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/1498 ,  H05K7/2039 ,  H05K7/20709 ,  H05K7/20727 ,  H05K7/20736 ,  H05K7/20745 ,  H05K7/20836 ,  H05K13/0486 ,  H05K2201/066 ,  H05K2201/10121 ,  H05K2201/10159 ,  H05K2201/10189 ,  Y10S901/01

Abstract: Technologies for performing low-latency decompression include a managed node to parse, in response to a determination that a read tree descriptor does not match a cached tree descriptor, the read tree descriptor to construct one or more tables indicative of codes in compressed data. Each code corresponds to a different symbol. The managed node is further to decompress the compressed data with the one or more tables and store the one or more tables in association with the read tree descriptor in a cache memory for subsequent use.

公开(公告)号：US20180024752A1

公开(公告)日：2018-01-25

申请号：US15396017

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Steven C. Miller ,  Vinodh Gopal ,  Kirk S. Yap ,  James D. Guilford ,  Wajdi K. Feghali

IPC: G06F3/06

CPC classification number: H04Q11/0005 ,  B25J15/0014 ,  B65G1/0492 ,  G02B6/3882 ,  G02B6/3893 ,  G02B6/3897 ,  G02B6/4292 ,  G02B6/4452 ,  G05D23/1921 ,  G05D23/2039 ,  G06F1/183 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0688 ,  G06F3/0689 ,  G06F8/65 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/4401 ,  G06F9/5016 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5072 ,  G06F9/5077 ,  G06F9/544 ,  G06F11/141 ,  G06F11/3414 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/10 ,  G06F12/109 ,  G06F12/1408 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/409 ,  G06F13/42 ,  G06F13/4282 ,  G06F15/8061 ,  G06F16/9014 ,  G06F2209/5019 ,  G06F2209/5022 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/7207 ,  G06Q10/06 ,  G06Q10/06314 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  G07C5/008 ,  G08C17/02 ,  G08C2200/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1072 ,  G11C11/56 ,  G11C14/0009 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/3086 ,  H03M7/40 ,  H03M7/4031 ,  H03M7/4056 ,  H03M7/4081 ,  H03M7/6005 ,  H03M7/6023 ,  H04B10/25 ,  H04B10/2504 ,  H04L9/0643 ,  H04L9/14 ,  H04L9/3247 ,  H04L9/3263 ,  H04L12/2809 ,  H04L29/12009 ,  H04L41/024 ,  H04L41/046 ,  H04L41/0813 ,  H04L41/082 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/145 ,  H04L41/147 ,  H04L41/5019 ,  H04L43/065 ,  H04L43/08 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L43/16 ,  H04L45/02 ,  H04L45/52 ,  H04L47/24 ,  H04L47/38 ,  H04L47/765 ,  H04L47/782 ,  H04L47/805 ,  H04L47/82 ,  H04L47/823 ,  H04L49/00 ,  H04L49/15 ,  H04L49/25 ,  H04L49/357 ,  H04L49/45 ,  H04L49/555 ,  H04L67/02 ,  H04L67/10 ,  H04L67/1004 ,  H04L67/1008 ,  H04L67/1012 ,  H04L67/1014 ,  H04L67/1029 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/12 ,  H04L67/16 ,  H04L67/306 ,  H04L67/34 ,  H04L69/04 ,  H04L69/329 ,  H04Q1/04 ,  H04Q11/00 ,  H04Q11/0003 ,  H04Q11/0062 ,  H04Q11/0071 ,  H04Q2011/0037 ,  H04Q2011/0041 ,  H04Q2011/0052 ,  H04Q2011/0073 ,  H04Q2011/0079 ,  H04Q2011/0086 ,  H04Q2213/13523 ,  H04Q2213/13527 ,  H04W4/023 ,  H04W4/80 ,  H05K1/0203 ,  H05K1/181 ,  H05K5/0204 ,  H05K7/1418 ,  H05K7/1421 ,  H05K7/1422 ,  H05K7/1442 ,  H05K7/1447 ,  H05K7/1461 ,  H05K7/1485 ,  H05K7/1487 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/1498 ,  H05K7/2039 ,  H05K7/20709 ,  H05K7/20727 ,  H05K7/20736 ,  H05K7/20745 ,  H05K7/20836 ,  H05K13/0486 ,  H05K2201/066 ,  H05K2201/10121 ,  H05K2201/10159 ,  H05K2201/10189 ,  Y02D10/14 ,  Y02D10/151 ,  Y02P90/30 ,  Y04S10/54 ,  Y10S901/01

Abstract: Technologies for low-latency compression in a data center are disclosed. In the illustrative embodiment, a storage sled compresses data with a low-latency compression algorithm prior to storing the data. The latency of the compression algorithm is less than the latency of the storage device, so that the latency of the storage and retrieval times are not significantly affected by the compression and decompression. In other embodiments, a compute sled may compress data with a low-latency compression algorithm prior to sending the data to a storage sled.

公开(公告)号：US20180011796A1

公开(公告)日：2018-01-11

申请号：US15201697

申请日：2016-07-05

Applicant: Intel Corporation

Inventor： James D. Guilford ,  Vinodh Gopal ,  Kirk S. Yap

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/10 ,  G06F12/023 ,  G06F2212/251 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/6005 ,  H03M7/6023

Abstract: A processor includes a memory hierarchy, buffer, and a decompressor. The decompressor includes circuitry to read elements to be decompressed according to a compression scheme, parse the elements to identify literals and matches, and, with the literals and matches, generate an intermediate token stream formatted for software-based copying of the literals and matches to produce decompressed data. The intermediate token stream is to include a format for multiple tokens that are to be written in parallel with each other, and another format for tokens that include a data dependency upon themselves.

公开(公告)号：US09853660B1

公开(公告)日：2017-12-26

申请号：US15468061

申请日：2017-03-23

Applicant: INTEL CORPORATION

Inventor： Vinodh Gopal ,  Kirk S. Yap ,  Daniel F. Cutter ,  James D. Guilford ,  Wajdi K. Feghali

IPC: H03M7/00 ,  H03M7/34 ,  H03M7/30 ,  H03M7/40

CPC classification number: H03M7/3086 ,  H03M7/40 ,  H03M7/6023

Abstract: Techniques and apparatus for parallel data compression are described. An apparatus to provide parallel data compression may include at least one memory and logic for a compression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to provide at least one data input sequence to a plurality of compression components, determine compression information for the plurality of compression components, and perform a compression process on the at least one data input sequence via the plurality of compression components to generate at least one data output sequence, the plurality of compression components to perform the compression process in parallel based on the compression information.