公开(公告)号：US09722021B2

公开(公告)日：2017-08-01

申请号：US14843082

申请日：2015-09-02

Applicant: Texas Instruments Incorporated

Inventor： Bruce Lynn Pickelsimer ,  Patrick Robert Smith ,  Terry James Bordelon, Jr.

IPC: H01L21/225 ,  H01L29/06 ,  H01L29/788 ,  H01L29/66 ,  H01L21/306 ,  H01L21/283

CPC classification number: H01L29/0649 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/30604 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/788

Abstract: An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.

公开(公告)号：US20170200798A1

公开(公告)日：2017-07-13

申请号：US14990059

申请日：2016-01-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jin-Dah Chen ,  Han-Wei Wu ,  Ming-Feng Shieh

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/308 ,  H01L21/283

CPC classification number: H01L29/4236 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/32139 ,  H01L21/823456 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming a first, a second and a third trenches extending through a dielectric layer over a substrate, forming a material layer in the first, the second and the third trenches, forming a sacrificial layer to fully fill in the remaining first and the second trenches, recessing the sacrificial layer in the first trench and the second trench, recessing the material layer in the first trench and in the second trench. After recessing the material layer, a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the first trench and a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the second trench. The method also includes removing the remaining sacrificial layer in the first trench and the second trench.

公开(公告)号：US09704742B2

公开(公告)日：2017-07-11

申请号：US13604452

申请日：2012-09-05

Applicant: Kazuyuki Fujiwara ,  Kazunori Inoue ,  Takahito Yamabe

Inventor： Kazuyuki Fujiwara ,  Kazunori Inoue ,  Takahito Yamabe

IPC: H01L29/786 ,  H01L21/283 ,  H01L21/768 ,  H01L29/45 ,  H01L29/49 ,  H01L27/12

CPC classification number: H01L21/76838 ,  H01L21/283 ,  H01L27/1244 ,  H01L29/458 ,  H01L29/4908

Abstract: An Al wiring film having a tapered shape is obtained easily and in a stable manner. An Al wiring film has a double-layer structure including a first Al alloy layer made of Al or an Al alloy, and a second Al alloy layer laid on the first Al alloy layer and having a composition different from a composition of the first Al alloy layer by containing at least one element of Ni, Pd, and Pt. The second Al alloy layer is etched by an alkaline chemical solution used in a developing process of a photoresist, and an end portion of the second Al alloy layer recedes from an end portion of the photoresist. Thereafter, by performing wet etching using the photoresist as a mask, a cross section of the Al wiring film becomes a tapered shape.

公开(公告)号：US09698101B2

公开(公告)日：2017-07-04

申请号：US14839108

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H01L23/528 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US09685508B2

公开(公告)日：2017-06-20

申请号：US14946718

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  G05F3/02 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/225 ,  H01L21/283 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20170162541A1

公开(公告)日：2017-06-08

申请号：US15437193

申请日：2017-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Feng Chen ,  Kai-Chiang Wu ,  Chun-Lin Lu ,  Hung-Jui Ko

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/10 ,  H01L23/147 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/6024 ,  H01L2223/5446 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11318 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.

公开(公告)号：US09673115B2

公开(公告)日：2017-06-06

申请号：US14933107

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Dieter Lipp ,  Stefan Richter

IPC: H01L29/10 ,  H01L21/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/283

CPC classification number: H01L21/283 ,  H01L21/02488 ,  H01L22/34 ,  H01L29/0653 ,  H01L29/78

Abstract: The present disclosure provides a test structure which includes an SOI substrate having an active semiconductor layer, a buried insulating material layer, and a base substrate, wherein the active semiconductor layer is formed on the buried insulating material layer, which, in turn, is formed on the base substrate. The test structure further includes a contact which is formed on the active semiconductor layer and electrically coupled to the active semiconductor layer. Herein, the contact has a tip portion extending through the active semiconductor layer into the buried insulating material layer.

公开(公告)号：US09660055B2

公开(公告)日：2017-05-23

申请号：US15057800

申请日：2016-03-01

Applicant: Infineon Technologies Austria AG

Inventor： Martin Poelzl ,  Till Schloesser ,  Andreas Meiser

IPC: H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/225 ,  H01L21/283 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66704 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections.

公开(公告)号：US20170141209A1

公开(公告)日：2017-05-18

申请号：US15419315

申请日：2017-01-30

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Dalong Zhao ,  Teymur Bakhishev ,  Lance Scudder ,  Paul E. Gregory ,  Michael Duane ,  U.C. Sridharan ,  Pushkar Ranade ,  Lucian Shifren ,  Thomas Hoffmann

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/283

CPC classification number: H01L29/66537 ,  H01L21/265 ,  H01L21/283 ,  H01L21/823412 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66477

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element

公开(公告)号：US20170140933A1

公开(公告)日：2017-05-18

申请号：US14942546

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/283 ,  H01L29/06

CPC classification number: H01L21/02603 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method includes forming a first semiconductor stack using an epitaxial growth process, the first semiconductor stack comprising a first plurality of semiconductor layers alternating with a second plurality of semiconductor layers, the first plurality of semiconductor layers comprising a first semiconductor material and the second plurality of semiconductor layers comprising a second semiconductor material that is different than the first semiconductor material. The method further includes patterning the first semiconductor stack to form a set of semiconductor stack features, forming isolation features between the semiconductor stack features, removing at least one of the semiconductor stack features, thereby forming at least one trench, and forming, within the trench, a second semiconductor stack using an epitaxial growth process, the second semiconductor stack having different characteristics than the first semiconductor stack.