公开(公告)号：US20170155381A1

公开(公告)日：2017-06-01

申请号：US15431374

申请日：2017-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Raimondi ,  Edoardo Botti

IPC: H03K5/1252 ,  H03K4/08 ,  H03K7/08

CPC classification number: H03K5/1252 ,  H03F1/26 ,  H03F1/32 ,  H03F3/217 ,  H03K4/08 ,  H03K5/01 ,  H03K7/08

Abstract: A method is for reducing pulse skipping from a characteristic affecting a modulating signal input to an integrator of a pulse width modulation (PWM) modulator, together with a square wave carrier signal for generating a triangular waveform of the PWM modulator. The method may include creating a broad synchronous peak at vertexes of the triangular waveform output by the integrator.

公开(公告)号：US20170152186A1

公开(公告)日：2017-06-01

申请号：US15192648

申请日：2016-06-24

Applicant: STMicroelectronics S.R.L.

Inventor： Angela Cimmino ,  Giovanna Salzillo ,  Valeria Casuscelli ,  Andrea Di Matteo

IPC: C04B35/468 ,  B05D3/00 ,  C04B35/64 ,  C09D1/00 ,  C04B35/622

CPC classification number: C04B35/4682 ,  C04B35/465 ,  C04B35/49 ,  C04B35/62222 ,  C04B35/624 ,  C04B35/6264 ,  C04B35/62675 ,  C04B35/62685 ,  C04B35/6325 ,  C04B35/63444 ,  C04B35/63488 ,  C04B2235/3208 ,  C04B2235/3215 ,  C04B2235/3232 ,  C04B2235/3234 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3262 ,  C04B2235/3293 ,  C04B2235/441 ,  C04B2235/449 ,  C04B2235/72 ,  C04B2235/768 ,  C04B2235/81 ,  C09D1/00 ,  C09D5/03 ,  C09D7/61

Abstract: The present disclosure relates to a precursor solution for the preparation of a ceramic of the BZT-αBXT type, where X is selected from Ca, Sn, Mn, and Nb, and a is a molar fraction selected in the range between 0.10 and 0.90, said solution comprising: 1) at least one barium precursor compound; 2) a precursor compound selected from the group consisting of at least one calcium compound, at least one tin compound, at least one manganese compound, and at least one niobium compound; 3) at least one anhydrous precursor compound of zirconium; 4) at least one anhydrous precursor compound of titanium; 5) a solvent selected from the group consisting of a polyol and mixtures of a polyol and a secondary solvent selected from the group consisting of alcohols, carboxylic acids, esters, ketones, ethers, and mixtures thereof; and 6) a chelating agent, as well as method of using the same.

公开(公告)号：US20170151784A1

公开(公告)日：2017-06-01

申请号：US15191154

申请日：2016-06-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Domenico Giusti ,  Lorenzo Colombo ,  Carlo Luigi Prelini ,  Mauro Cattaneo

IPC: B41J2/14 ,  B41J2/16

CPC classification number: B41J2/14201 ,  B41J2/14233 ,  B41J2/1607 ,  B41J2/161 ,  B41J2/1623 ,  B41J2/1626 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1642 ,  B41J2002/14241 ,  B41J2002/14411 ,  B41J2202/12

Abstract: A fluid ejection device, comprising: a first semiconductor body including an actuator, which is operatively coupled to a chamber for containing the fluid and is configured to cause ejection of the fluid; and a channel for inlet of the fluid, which extends in a first direction and has a section having a first dimension; and a second semiconductor body, which is coupled to the first semiconductor body and has an ejection nozzle configured to expel the fluid. The second semiconductor body further comprises a first restriction channel, which is fluidically coupled to the inlet channel, extends in a second direction orthogonal to the first direction and has a respective section with a second dimension smaller than the first dimension so as to form a restriction between the inlet channel and the chamber.

公开(公告)号：US20170147416A1

公开(公告)日：2017-05-25

申请号：US14951639

申请日：2015-11-25

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Om RANJAN ,  Fabio Enrico Carlo DISEGNI

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/08 ,  G06F11/1004 ,  G06F11/16 ,  G11B2020/1843 ,  G11C29/02 ,  G11C29/04 ,  G11C29/42

Abstract: An electronic device includes a memory having memory locations being subject to transient faults and permanent faults, and a fault detection circuit coupled to the memory. The fault detection circuit is configured to read the memory locations at a first time, and determine a first fault count and fault map signature including the transient and permanent faults at the first time based upon reading the plurality of memory locations, and to store the first fault count and fault map signature. The fault detection circuit is configured to read the memory locations at a second time and determine a second fault count and fault map signature including the transient and permanent faults at the second time based upon reading the memory locations, and compare the stored first fault count and fault map signature with the second fault count and fault map signature to determine a permanent fault count.

公开(公告)号：US20170141775A1

公开(公告)日：2017-05-18

申请号：US15163142

申请日：2016-05-24

Applicant: STMicroelectronics S.R.L.

Inventor： Giovanni Caggegi ,  Francesco Pulvirenti ,  Giuseppe Cantone ,  Vincenzo Palumbo

IPC: H03K17/687 ,  H01L29/78 ,  H03K5/24

CPC classification number: H03K17/687 ,  H01L29/7816 ,  H03K5/24 ,  H03K17/04123 ,  H03K17/063 ,  H03K17/74 ,  H03K2017/066

Abstract: A circuit provides a high-voltage low-drop diode-like conductive path between a DC voltage supply terminal and a bootstrap terminal in charging a supply capacitor for driving a power switch with the capacitor set between the bootstrap terminal and an output terminal alternatively switchable between a low voltage and a high voltage DC voltage. In an embodiment, the circuit includes first and second transistors such as LDMOS depletion transistors with the first transistor set in a cascode arrangement between the bootstrap terminal and the DC voltage supply terminal and the second transistor coupled with a sense comparator for comparing the voltage at the bootstrap terminal with the voltage at said DC voltage supply terminal. The first and second transistors have common control terminals coupled with the DC voltage supply terminal and common coupling terminals to the bootstrap terminal.

公开(公告)号：US20170141218A1

公开(公告)日：2017-05-18

申请号：US15156740

申请日：2016-05-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L29/205 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

公开(公告)号：US20170133307A1

公开(公告)日：2017-05-11

申请号：US15159212

申请日：2016-05-19

Applicant: STMicroelectronics S.r.l.

Inventor： Federico Giovanni Ziglioli

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0538 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/15747 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0295 ,  H05K1/112 ,  H05K3/107 ,  H05K3/205 ,  H05K3/4015 ,  H05K3/4046 ,  H05K2201/09409 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/0338 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/1189 ,  H05K2203/143 ,  H05K2203/1461 ,  H05K2203/1476 ,  H05K2203/308 ,  H01L2224/45099

Abstract: A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.

公开(公告)号：US09646713B2

公开(公告)日：2017-05-09

申请号：US15140023

申请日：2016-04-27

Applicant: STMicroelectronics S.r.l.

Inventor： Ignazio Bruno Mirabella ,  Salvatore Pappalardo ,  Calogero Ribellino ,  Alessandro Nicolosi

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C11/4125 ,  G11C17/16 ,  H03K3/02335 ,  H03K19/00338 ,  H03K19/17764

Abstract: A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

公开(公告)号：US09642244B2

公开(公告)日：2017-05-02

申请号：US13841273

申请日：2013-03-15

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana

IPC: B01L3/14 ,  H05K1/02 ,  B01L3/00 ,  H05K3/30 ,  H05K1/18

CPC classification number: H05K1/0298 ,  B01L3/502707 ,  B01L3/502715 ,  B01L2200/027 ,  B01L2200/12 ,  B01L2300/0816 ,  B01L2300/0887 ,  B01L2300/12 ,  H05K1/0272 ,  H05K1/181 ,  H05K3/30 ,  H05K2201/10083 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T137/0318

Abstract: An embodiment of a micro-electro-mechanical system of the MEMS type comprising at least one micro-electro-mechanical device of the MEMS type and one junction with a duct suitable to being associated with an external apparatus. Said junction being a printed circuit board PCB comprising at least two layers with juxtaposed faces, a channel being present in at least one face of at least one of said at least two layers suitable for realizing the duct with the juxtaposition of the other face of at least another one of at least two layers.

公开(公告)号：US09640506B2

公开(公告)日：2017-05-02

申请号：US14228370

申请日：2014-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： Federico Giovanni Ziglioli

IPC: H01L23/00 ,  B81C1/00 ,  H01L21/56 ,  H01L25/065 ,  G01L9/00 ,  G01L19/00 ,  H01L23/31

CPC classification number: H01L24/45 ,  B81C1/0023 ,  G01L9/0044 ,  G01L19/0076 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/16145 ,  H01L2224/2405 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/45032 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48611 ,  H01L2224/48711 ,  H01L2224/48811 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/8293 ,  H01L2224/85205 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/43 ,  H01L2924/01029

Abstract: An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled to the integrated electronic components; b) attaching at least one conductive ribbon to at least one contact pad of each chip; c) covering the main surface of the semiconductor material wafer and the at least one conductive ribbon with a layer of plastic material; d) lapping an exposed surface of the layer of plastic material to remove a portion of the plastic material layer at least to uncover portions of the at least one conductive ribbon, and e) sectioning the semiconductor material wafer to separate the chips.