公开(公告)号：US10044390B2

公开(公告)日：2018-08-07

申请号：US15216615

申请日：2016-07-21

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Chengjie Zuo ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Shiqun Gu ,  Jonghae Kim ,  David Berdy

IPC: H01L23/28 ,  H03H7/46 ,  H04B1/401 ,  H05K1/18 ,  H04B1/16 ,  H01L27/01 ,  H01L49/02 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48

Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

公开(公告)号：US09922956B2

公开(公告)日：2018-03-20

申请号：US14498965

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey Lan ,  Wenyue Zhang ,  Yang Du ,  Yong Ju Lee ,  Shiqun Gu ,  Jing Xie

IPC: H01L25/065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/683 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00 ,  H01L27/06 ,  H01L21/822

CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release.

公开(公告)号：US20180062617A1

公开(公告)日：2018-03-01

申请号：US15247803

申请日：2016-08-25

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Je-Hsiung Lan ,  Chengjie Zuo ,  David Berdy ,  Jonghae Kim ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Shiqun Gu

IPC: H03H9/205 ,  H01L41/332 ,  H03H9/54

CPC classification number: H03H9/205 ,  H01L41/332 ,  H03H3/04 ,  H03H9/173 ,  H03H9/54 ,  H03H2003/021 ,  H03H2003/0435 ,  H03H2003/0442 ,  H03H2003/0471

Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.

公开(公告)号：US09881859B2

公开(公告)日：2018-01-30

申请号：US14273882

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Shiqun Gu ,  Ratibor Radojcic

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/522 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/528 ,  H01L21/311 ,  H05K1/09 ,  H05K1/11 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/31127 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/20648 ,  H01L2924/3511 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09563 ,  H01L2924/014 ,  H01L2224/81

Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

公开(公告)号：US20180026666A1

公开(公告)日：2018-01-25

申请号：US15216615

申请日：2016-07-21

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Chengjie Zuo ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Shiqun Gu ,  Jonghae Kim ,  David Berdy

IPC: H04B1/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66 ,  H01L27/01 ,  H01L49/02

CPC classification number: H04B1/1638 ,  H01F17/0013 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/64 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L27/01 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2223/6688 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H04B1/006 ,  H05K1/165 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/09536 ,  H05K2201/097

Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

公开(公告)号：US09799628B2

公开(公告)日：2017-10-24

申请号：US15043484

申请日：2016-02-12

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14151 ,  H01L2224/14155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1624 ,  H01L2224/171 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/81 ,  H01L21/76898

Abstract: Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first plane, a second die located above the first die in a second plane with a portion extending past the first die, a third die located above the first die in the second plane with a portion extending past the first die, a fourth die located above the second die and the third die in a third plane with a portion extending past the second die and the third die, and a fifth die located above the second die and the third die in the third plane with a portion extending past the second die and the third die.

公开(公告)号：US09768161B2

公开(公告)日：2017-09-19

申请号：US14856873

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Rongtian Zhang ,  Lew Chua-Eoan ,  Shiqun Gu

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L27/13 ,  H01L49/02 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/86 ,  H01L29/66795

Abstract: A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.

公开(公告)号：US09768109B2

公开(公告)日：2017-09-19

申请号：US14861958

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L23/498 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/304 ,  H01L27/088 ,  H01L27/12 ,  H01L23/66 ,  H01L21/306

CPC classification number: H01L27/1203 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/66 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1266 ,  H01L29/1087 ,  H01L29/66772

Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

公开(公告)号：US09583460B2

公开(公告)日：2017-02-28

申请号：US14181371

申请日：2014-02-14

Applicant: QUALCOMM Incorporated

Inventor： Urmi Ray ,  Shiqun Gu

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/568 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24137 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/014

Abstract: Some features pertain to an integrated device that includes a dielectric layer configured as a base for the integrated device, several redistribution metal layers in the dielectric layer, a first wafer level die coupled to a first surface of the dielectric layer, and a second wafer level die coupled to the first wafer level die. The dielectric layer includes several dielectric layers. In some implementations, the first wafer level die is coupled to the redistribution metal layers through a first set of interconnects. In some implementations, the first wafer level die includes several through substrate vias (TSVs). In some implementations, the second wafer level die is coupled to the redistribution metal layers through a first set of interconnects, the TSVs, a second set of interconnects, and a set of solder balls. In some implementations, the integrated device includes an encapsulation layer that encapsulates the first and second wafer level dies.

Abstract translation: 一些特征涉及一种集成器件，其包括被配置为用于集成器件的基极的介质层，介电层中的几个再分布金属层，耦合到介电层的第一表面的第一晶片级管芯，以及第二晶片级 模具耦合到第一晶片级模具。 电介质层包括几个电介质层。 在一些实施方案中，第一晶片级管芯通过第一组互连件耦合到再分布金属层。 在一些实施方案中，第一晶片级管芯包括多个通过衬底通孔（TSV）。 在一些实施方案中，第二晶片级管芯通过第一组互连，TSV，第二组互连和一组焊球耦合到再分布金属层。 在一些实现中，集成器件包括封装第一和第二晶片级管芯的封装层。

公开(公告)号：US09355963B2

公开(公告)日：2016-05-31

申请号：US14498076

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Jae Sik Lee ,  Hong Bok We ,  Young Kyu Song ,  Chin-Kwan Kim ,  Kyu-Pyung Hwang ,  Shiqun Gu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括在一侧具有第一再分布层的基底，在与第一再分布层相反的一侧上附接到基部的第一和第二并排裸片，附接到主动侧的插入件 以提供第一和第二管芯之间的互连，从第一和第二管芯延伸到在与第一再分布层相对的封装的表面上的第二再分配层的多个管芯通孔，以及多个 在第一和第二再分配层之间延伸穿过包装的通孔。