公开(公告)号：US20130119534A1

公开(公告)日：2013-05-16

申请号：US13298183

申请日：2011-11-16

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/498

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02126 ,  H01L2224/02235 ,  H01L2224/0401 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06131 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/1312 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012

Abstract: A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering.

Abstract translation: 形成靠近用于将焊料凸块耦合到半导体管芯的导电接合焊盘的形貌特征。 地形特征与导电接合垫隔开间隙。 在一个实施例中，形貌特征形成在稍微超出焊料凸块周边的位置处，其中凸块的边缘垂直对齐，以将导电接合焊盘与形貌特征分开。 形貌特征提供了设置在半导体管芯上的非导电层的厚度增强和导电接合焊盘和应力缓冲。

公开(公告)号：US08298929B2

公开(公告)日：2012-10-30

申请号：US12960110

申请日：2010-12-03

Applicant: Timothy H. Daubenspeck ,  Gary Lafontant ,  Ekta Misra ,  David L. Questad ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Thomas A. Wassick ,  Steven L. Wright

Inventor： Timothy H. Daubenspeck ,  Gary Lafontant ,  Ekta Misra ,  David L. Questad ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Thomas A. Wassick ,  Steven L. Wright

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13006 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3511 ,  Y02P90/265 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.

Abstract translation: 提供半导体结构，制造方法和设计结构。 该结构包括与芯片的下面的金属焊盘接触形成的至少一个偏移月牙形焊料通孔。 至少一个偏移月牙形通孔相对于下面的金属焊盘和下面的金属层中的至少一个与芯片的与下面的金属层电接触的互连直接电接触而偏移。

公开(公告)号：US20120146186A1

公开(公告)日：2012-06-14

申请号：US12962722

申请日：2010-12-08

Applicant: Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

Inventor： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC: H01L27/06 ,  H01L21/02

CPC classification number: H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L27/0211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

Abstract translation: 制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。 每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。 最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。 一个电阻器被包含在最上层的上方的层中。 垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

公开(公告)号：US20120126405A1

公开(公告)日：2012-05-24

申请号：US13361232

申请日：2012-01-30

Applicant: Timothy Harrison Daubenspeck ,  Timothy D. Sullivan

Inventor： Timothy Harrison Daubenspeck ,  Timothy D. Sullivan

IPC: H01L23/498

CPC classification number: H01L23/488 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45147 ,  H01L2224/48824 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.

Abstract translation: 制作结构的结构和方法。 所述结构包括结构，包括：在衬底上延伸的有机介电钝化层; 在所述有机介电钝化层的顶表面上的导电电流扩散焊盘; 导电焊料凸块焊盘，其在电流扩散焊盘的顶表面上包括一层或多层; 以及包含锡的导电焊料凸块，所述焊料凸块在所述焊料凸块焊盘的顶表面上，所述电流扩散焊盘包括一个或多个层，所述一个或多个层中的至少一个由不会形成 金属间化合物与锡或一层或多层中的至少一层是对锡的扩散阻挡层并且与焊料凸块相邻的材料。

公开(公告)号：US20120108015A1

公开(公告)日：2012-05-03

申请号：US13347087

申请日：2012-01-10

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Marie-Claude Paquet ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Marie-Claude Paquet ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/56 ,  H01L21/768

CPC classification number: H01L21/56 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/743 ,  H01L24/97 ,  H01L29/0657 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Abstract translation: 底部填充流动引导结构及其使用方法具有模块。 特别地，底部填充流动引导结构与基底一体化并且被构造成防止在毛细管底部填充过程期间发生空气滞留。

公开(公告)号：US07985671B2

公开(公告)日：2011-07-26

申请号：US12344774

申请日：2008-12-29

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05019 ,  H01L2224/05027 ,  H01L2224/05088 ,  H01L2224/05096 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.

Abstract translation: 具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。 该方法包括在电介质层中形成上布线层，并在上布线层上淀积一层或多层介电层。 该方法还包括在延伸到上布线层的一个或多个电介质层中形成多个离散的沟槽。 该方法还包括在多个离散的沟槽中沉积限制极限的冶金或凸块下的冶金，以形成与上部绞合层接触的离散的金属岛。 形成与多个离散金属岛电连接的焊料凸块。

公开(公告)号：US20110006422A1

公开(公告)日：2011-01-13

申请号：US12458441

申请日：2009-07-13

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/498 ,  H01L21/3205 ,  G06F17/50

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/03005 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05016 ,  H01L2224/05019 ,  H01L2224/05027 ,  H01L2224/05552 ,  H01L2224/05563 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Controlled collapse chip connection (C4) structures and methods of manufacture, and more specifically to structures and methods to improve lead-free C4 interconnect reliability. A structure includes a ball limited metallization (BLM) layer and a controlled collapse chip connection (C4) solder ball formed on the BLM layer. Additionally, the structure includes a final metal pad layer beneath the BLM layer and a cap layer beneath the final metal pad layer. Furthermore, the structure includes an air gap formed beneath the C4 solder ball between the final metal pad layer and one of the BLM layer and the cap layer.

Abstract translation: 控制崩溃芯片连接（C4）结构和制造方法，更具体地说是提高无铅C4互连可靠性的结构和方法。 一种结构包括球限制金属化（BLM）层和形成在BLM层上的受控崩溃芯片连接（C4）焊球。 此外，该结构包括在BLM层下面的最终金属垫层和在最终金属垫层下面的盖层。 此外，该结构包括在最终金属焊盘层和BLM层和盖层之一内的C4焊球之下形成的气隙。

公开(公告)号：US20100164116A1

公开(公告)日：2010-07-01

申请号：US12344838

申请日：2008-12-29

Applicant: Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

Inventor： Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

IPC: H01L23/52 ,  H01L21/4763 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.

Abstract translation: 在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。 衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。 所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。 或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触 重叠变化。

公开(公告)号：US20100038780A1

公开(公告)日：2010-02-18

申请号：US12190612

申请日：2008-08-13

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Marie-Claude Paquet ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Marie-Claude Paquet ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/743 ,  H01L24/97 ,  H01L29/0657 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Abstract translation: 底部填充流动引导结构及其使用方法具有模块。 特别地，底部填充流动引导结构与基底一体化并且被构造成防止在毛细管底部填充过程期间发生空气滞留。

公开(公告)号：US07601602B2

公开(公告)日：2009-10-13

申请号：US11481514

申请日：2006-07-06

Applicant: John M. Aitken ,  Fen Chen ,  Timothy D. Sullivan

Inventor： John M. Aitken ,  Fen Chen ,  Timothy D. Sullivan

IPC: H01L21/04

CPC classification number: H01L28/20 ,  H01L27/101

Abstract: An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.

Abstract translation: 一种片上超小型可编程半导体电阻器件及器件结构及其制造方法。 每个半导体电阻器件结构由表现出精确电阻值的一个或多个导电连接的埋沟槽型电阻器元件形成。 至少两个半导体电阻器件结构可以通过一个或多个保险丝器件的中间串联或并联配置连接，该熔丝器件可以被吹制以实现期望的总电阻值。